/******************************************************************************
 * Privete Paresent Header
 ******************************************************************************/
#ifndef __DRV_L1_SFR_H__
#define __DRV_L1_SFR_H__

/******************************************************************************
 * Session: GPIO SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: GPIO SFR
 ******************************************************************************/
/******************************************************************************
 * GPIO: 0xC0000000
 ******************************************************************************/
#define R_IOA_I_DATA	(*((volatile INT32U *) 0xC0000000))
#define R_IOA_O_DATA	(*((volatile INT32U *) 0xC0000004))
#define R_IOA_DIR		(*((volatile INT32U *) 0xC0000008))
#define R_IOA_ATT		(*((volatile INT32U *) 0xC000000C))
#define R_IOA_DRV		(*((volatile INT32U *) 0xC0000010))
#define R_IOB_I_DATA	(*((volatile INT32U *) 0xC0000020))
#define R_IOB_O_DATA	(*((volatile INT32U *) 0xC0000024))
#define R_IOB_DIR		(*((volatile INT32U *) 0xC0000028))
#define R_IOB_ATT		(*((volatile INT32U *) 0xC000002C))
#define R_IOB_DRV		(*((volatile INT32U *) 0xC0000030))
#define R_IOC_I_DATA	(*((volatile INT32U *) 0xC0000040))
#define R_IOC_O_DATA	(*((volatile INT32U *) 0xC0000044))
#define R_IOC_DIR		(*((volatile INT32U *) 0xC0000048))
#define R_IOC_ATT		(*((volatile INT32U *) 0xC000004C))
#define R_IOC_DRV		(*((volatile INT32U *) 0xC0000050))
#define R_IOD_I_DATA	(*((volatile INT32U *) 0xC0000060))
#define R_IOD_O_DATA	(*((volatile INT32U *) 0xC0000064))
#define R_IOD_DIR		(*((volatile INT32U *) 0xC0000068))
#define R_IOD_ATT		(*((volatile INT32U *) 0xC000006C))
#define R_IOD_DRV		(*((volatile INT32U *) 0xC0000070))
#define R_IOE_I_DATA	(*((volatile INT32U *) 0xC0000080))
#define R_IOE_O_DATA	(*((volatile INT32U *) 0xC0000084))
#define R_IOE_DIR		(*((volatile INT32U *) 0xC0000088))
#define R_IOE_ATT		(*((volatile INT32U *) 0xC000008C))
#define R_IOE_DRV		(*((volatile INT32U *) 0xC0000090))
#define R_IOF_I_DATA	(*((volatile INT32U *) 0xC00000A0))
#define R_IOF_O_DATA	(*((volatile INT32U *) 0xC00000A4))
#define R_IOF_DIR		(*((volatile INT32U *) 0xC00000A8))
#define R_IOF_ATT		(*((volatile INT32U *) 0xC00000AC))
#define R_IOF_DRV		(*((volatile INT32U *) 0xC00000B0))
#define R_IOG_I_DATA	(*((volatile INT32U *) 0xC00000C0))
#define R_IOG_O_DATA	(*((volatile INT32U *) 0xC00000C4))
#define R_IOG_DIR		(*((volatile INT32U *) 0xC00000C8))
#define R_IOG_ATT		(*((volatile INT32U *) 0xC00000CC))
#define R_IOG_DRV		(*((volatile INT32U *) 0xC00000D0))
#define R_IOH_I_DATA	(*((volatile INT32U *) 0xC00000E0))
#define R_IOH_O_DATA	(*((volatile INT32U *) 0xC00000E4))
#define R_IOH_DIR		(*((volatile INT32U *) 0xC00000E8))
#define R_IOH_ATT		(*((volatile INT32U *) 0xC00000EC))
#define R_IOH_DRV		(*((volatile INT32U *) 0xC00000F0))
#define R_IOSMTSEL		(*((volatile INT32U *) 0xC0000100))
#define R_IOSRSEL		(*((volatile INT32U *) 0xC0000104))					/*Dominant add, 06/17/2008*/
#define R_IO_SWITCH_ND	(*((volatile INT32U *) 0xC0000108))
#define R_FUNPOS0		(*((volatile INT32U *) 0xC0000108))					/*Dominant add, 04/14/2008*/
#define R_KEYCH			(*((volatile INT32U *) 0xC0000110))
#define R_FUNPOS1		(*((volatile INT32U *) 0xC000010C))

//#define R_FUNPOS1		(*((volatile INT32U *) 0xC0000114))
#define R_FUNPOS3		(*((volatile INT32U *) 0xC0000118))
#define R_MEMCTRL		(*((volatile INT32U *) 0xC0000120))
#define R_MEM_DRV		(*((volatile INT32U *) 0xC0000124))
#define R_PWM_CTRL		(*((volatile INT32U *) 0xC0000134))
#define R_GPIOCTRL		(*((volatile INT32U *) 0xC0000114))					/*Dominant add, 04/18/2008*/
#define R_SYSMONICTRL	(*((volatile INT32U *) 0xC0000140))					/*Dominant add, 06/17/2008*/
#define R_ANALOG_CTRL	(*((volatile INT32U *) 0xC0000130))
#define R_PWMCTRL		(*((volatile INT32U *) 0xC0000134))
#define R_SYSMONI_CTRL	(*((volatile INT32U *) 0xC0000140))
#define R_SMONI0		(*((volatile INT32U *) 0xC0000150))
#define R_SMONI1		(*((volatile INT32U *) 0xC0000154))
#define R_XD_DCTRL		(*((volatile INT32U *) 0xC0000160))
#define R_XD_DCTRL1		(*((volatile INT32U *) 0xC0000164))
#define R_XA_DCTRL		(*((volatile INT32U *) 0xC0000168))
#define R_XA_DCTRL1		(*((volatile INT32U *) 0xC000016C))
#define R_OTR_DCTRL		(*((volatile INT32U *) 0xC0000170))
#define R_KEY_POS_EN    (*((volatile INT32U *) 0xC000017C))
#define R_IOA_DATA		R_IOA_I_DATA
#define R_IOA_BUFFER	R_IOA_O_DATA
#define R_IOA_ATTRIB	R_IOA_ATT
#define R_IOB_DATA		R_IOB_I_DATA
#define R_IOB_BUFFER	R_IOB_O_DATA
#define R_IOB_ATTRIB	R_IOB_ATT
#define R_IOC_DATA		R_IOC_I_DATA
#define R_IOC_BUFFER	R_IOC_O_DATA
#define R_IOC_ATTRIB	R_IOC_ATT
#define R_IOD_DATA		R_IOD_I_DATA
#define R_IOD_BUFFER	R_IOD_O_DATA
#define R_IOD_ATTRIB	R_IOD_ATT
#define R_IOE_DATA		R_IOE_I_DATA
#define R_IOE_BUFFER	R_IOE_O_DATA
#define R_IOE_ATTRIB	R_IOE_ATT
#define R_IOF_DATA		R_IOF_I_DATA
#define R_IOF_BUFFER	R_IOF_O_DATA
#define R_IOF_ATTRIB	R_IOF_ATT
#define R_IOG_DATA		R_IOG_I_DATA
#define R_IOG_BUFFER	R_IOG_O_DATA
#define R_IOG_ATTRIB	R_IOG_ATT
#define R_IOH_DATA		R_IOH_I_DATA
#define R_IOH_BUFFER	R_IOH_O_DATA
#define R_IOH_ATTRIB	R_IOH_ATT

/******************************************************************************
 * SPI Flash controller: 0xC0010000
 ******************************************************************************/
#define P_SPIFC_BASE		0xC0010000
#define R_SPIFC_MIO_CTRL	(*((volatile INT32U *) (P_SPIFC_BASE + 0x00)))
#define R_SPIFC_CMD			(*((volatile INT32U *) (P_SPIFC_BASE + 0x04)))
#define R_SPIFC_PARA		(*((volatile INT32U *) (P_SPIFC_BASE + 0x08)))
#define R_SPIFC_ADDRL		(*((volatile INT32U *) (P_SPIFC_BASE + 0x0C)))
#define R_SPIFC_ADDRH		(*((volatile INT32U *) (P_SPIFC_BASE + 0x10)))
#define R_SPIFC_TX_WD		(*((volatile INT32U *) (P_SPIFC_BASE + 0x14)))
#define R_SPIFC_RX_RD		(*((volatile INT32U *) (P_SPIFC_BASE + 0x18)))
#define R_SPIFC_TX_BC		(*((volatile INT32U *) (P_SPIFC_BASE + 0x1C)))
#define R_SPIFC_RX_BC		(*((volatile INT32U *) (P_SPIFC_BASE + 0x20)))
#define R_SPIFC_TIMING		(*((volatile INT32U *) (P_SPIFC_BASE + 0x24)))
#define R_SPIFC_OTHER		(*((volatile INT32U *) (P_SPIFC_BASE + 0x28)))
#define R_SPIFC_CTRL		(*((volatile INT32U *) (P_SPIFC_BASE + 0x2C)))

/******************************************************************************
 * Session: Timer1 SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Timer1 SFR
 ******************************************************************************/
/******************************************************************************
 * Timer1: 0xC0020000
 ******************************************************************************/
#define R_TIMERA_CTRL		(*((volatile INT32U *) 0xC0020000))
#define R_TIMERA_CCP_CTRL	(*((volatile INT32U *) 0xC0020004))
#define R_TIMERA_PRELOAD	(*((volatile INT32U *) 0xC0020008))
#define R_TIMERA_CCP_REG	(*((volatile INT32U *) 0xC002000C))
#define R_TIMERA_UPCOUNT	(*((volatile INT32U *) 0xC0020010))
#define R_TIMERA_CMPLOAD	(*((volatile INT32U *) 0xC0020014))
#define R_TIMERA_STATUS		(*((volatile INT32U *) 0xC002001C))
#define R_TIMERB_CTRL		(*((volatile INT32U *) 0xC0020020))
#define R_TIMERB_CCP_CTRL	(*((volatile INT32U *) 0xC0020024))
#define R_TIMERB_PRELOAD	(*((volatile INT32U *) 0xC0020028))
#define R_TIMERB_CCP_REG	(*((volatile INT32U *) 0xC002002C))
#define R_TIMERB_UPCOUNT	(*((volatile INT32U *) 0xC0020030))
#define R_TIMERB_CMPLOAD	(*((volatile INT32U *) 0xC0020034))
#define R_TIMERB_STATUS		(*((volatile INT32U *) 0xC002003C))
#define R_TIMERC_CTRL		(*((volatile INT32U *) 0xC0020040))
#define R_TIMERC_CCP_CTRL	(*((volatile INT32U *) 0xC0020044))
#define R_TIMERC_PRELOAD	(*((volatile INT32U *) 0xC0020048))
#define R_TIMERC_CCP_REG	(*((volatile INT32U *) 0xC002004C))
#define R_TIMERC_UPCOUNT	(*((volatile INT32U *) 0xC0020050))
#define R_TIMERC_CMPLOAD	(*((volatile INT32U *) 0xC0020054))
#define R_TIMERC_STATUS		(*((volatile INT32U *) 0xC002005C))
#define R_TIMERD_CTRL		(*((volatile INT32U *) 0xC0020060))
#define R_TIMERD_PRELOAD	(*((volatile INT32U *) 0xC0020068))
#define R_TIMERD_CCP_REG	(*((volatile INT32U *) 0xC002006C))
#define R_TIMERD_UPCOUNT	(*((volatile INT32U *) 0xC0020070))
#define R_TIMERD_CMPLOAD	(*((volatile INT32U *) 0xC0020074))
#define R_TIMERD_STATUS		(*((volatile INT32U *) 0xC002007C))
#define R_TIMERE_CTRL		(*((volatile INT32U *) 0xC0020080))
#define R_TIMERE_PRELOAD	(*((volatile INT32U *) 0xC0020088))
#define R_TIMERE_UPCOUNT	(*((volatile INT32U *) 0xC0020090))
#define R_TIMERE_CMPLOAD	(*((volatile INT32U *) 0xC0020094))
#define R_TIMERE_STATUS		(*((volatile INT32U *) 0xC002009C))
#define R_TIMERF_CTRL		(*((volatile INT32U *) 0xC00200A0))
#define R_TIMERF_PRELOAD	(*((volatile INT32U *) 0xC00200A8))
#define R_TIMERF_UPCOUNT	(*((volatile INT32U *) 0xC00200B0))
#define R_TIMERF_CMPLOAD	(*((volatile INT32U *) 0xC00200B4))
#define R_TIMERF_STATUS		(*((volatile INT32U *) 0xC00200BC))
#define R_TIMERG_CTRL		(*((volatile INT32U *) 0xC00200C0))
#define R_TIMERG_PRELOAD	(*((volatile INT32U *) 0xC00200C8))
#define R_TIMERG_CCP_REG	(*((volatile INT32U *) 0xC00200CC))
#define R_TIMERG_UPCOUNT	(*((volatile INT32U *) 0xC00200D0))
#define R_TIMERG_CMPLOAD	(*((volatile INT32U *) 0xC00200D4))
#define R_TIMERG_STATUS		(*((volatile INT32U *) 0xC00200DC))
#define R_TIMERH_CTRL		(*((volatile INT32U *) 0xC00200E0))
#define R_TIMERH_PRELOAD	(*((volatile INT32U *) 0xC00200E8))
#define R_TIMERH_CCP_REG	(*((volatile INT32U *) 0xC00200EC))
#define R_TIMERH_UPCOUNT	(*((volatile INT32U *) 0xC00200F0))
#define R_TIMERH_CMPLOAD	(*((volatile INT32U *) 0xC00200F4))
#define R_TIMERH_STATUS		(*((volatile INT32U *) 0xC00200FC))

/******************************************************************************
 * Session: Time Base SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Time Base SFR
 ******************************************************************************/
/******************************************************************************
 * Time Base: 0xC0030000
 ******************************************************************************/
#define R_TIMEBASEA_CTRL	(*((volatile INT32U *) 0xC0030000))
#define R_TIMEBASEB_CTRL	(*((volatile INT32U *) 0xC0030004))
#define R_TIMEBASEC_CTRL	(*((volatile INT32U *) 0xC0030008))
#define R_TIMEBASE_RESET	(*((volatile INT32U *) 0xC0030020))

/******************************************************************************
 * Session: RTC SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: RTC SFR
 ******************************************************************************/
/******************************************************************************
 * RTC: 0xC0040000
 ******************************************************************************/
#define RTC_BASE	((volatile INT32U *) 0xC0040000)

/******************************************************************************
 * Session: GPL32600 independent power RTC SFR
 * Layer: Driver Layer 1
 * Date:
 * Note: RTC SFR
 ******************************************************************************/
/******************************************************************************
 * RTC: 0xC0090000
 ******************************************************************************/
/*
#define R_RTC_IDPWR_CTRL				(*((volatile INT32U *) 0xC0090000))
#define R_RTC_IDPWR_CTRL_FLAG			(*((volatile INT32U *) 0xC0090004))
#define R_RTC_IDPWR_ADDR				(*((volatile INT32U *) 0xC0090008))
#define R_RTC_IDPWR_WDATA				(*((volatile INT32U *) 0xC009000C))
#define R_RTC_IDPWR_RDATA				(*((volatile INT32U *) 0xC0090010))
*/
/******************************************************************************
 * Session: Key Scan SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Key Scan SFR
 ******************************************************************************/
/******************************************************************************
 * Key Scan: 0xC0050000
 ******************************************************************************/
#define R_KEYSCAN_CTRL0		(*((volatile INT32U *) 0xC0050000))
#define R_KEYSCAN_CTRL1		(*((volatile INT32U *) 0xC0050004))
#define R_KEYSCAN_ADDR		(*((volatile INT32U *) 0xC0050008))
#define R_KEYSCAN_VELOCITY	(*((volatile INT32U *) 0xC005000C))
#define P_KEYSCAN_DATA0		((volatile INT32U *) 0xC0050020)
#define P_KEYSCAN_DATA1		((volatile INT32U *) 0xC0050024)
#define P_KEYSCAN_DATA2		((volatile INT32U *) 0xC0050028)
#define P_KEYSCAN_DATA3		((volatile INT32U *) 0xC005002c)
#define P_KEYSCAN_DATA4		((volatile INT32U *) 0xC0050030)
#define P_KEYSCAN_DATA5		((volatile INT32U *) 0xC0050034)
#define P_KEYSCAN_DATA6		((volatile INT32U *) 0xC0050038)
#define P_KEYSCAN_DATA7		((volatile INT32U *) 0xC005003C)
#define P_KEYSCAN_DATA8		((volatile INT32U *) 0xC0050040)
#define P_KEYSCAN_DATA9		((volatile INT32U *) 0xC0050044)
#define P_KEYSCAN_DATA10	((volatile INT32U *) 0xC0050048)

/******************************************************************************
 * Session: UART_IRDA SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: UART_IRDA SFR
 ******************************************************************************/
/******************************************************************************
 * UART0: 0xC0060000, UART1: 0xC0070000
 ******************************************************************************/
#define P_UART0_BASE		((volatile INT32U *) 0xC0060000)
#define R_UART0_DATA		(*((volatile INT32U *) 0xC0060000))
#define R_UART0_RX_STATUS	(*((volatile INT32U *) 0xC0060004))
#define R_UART0_CTRL		(*((volatile INT32U *) 0xC0060008))
#define R_UART0_BAUD_RATE	(*((volatile INT32U *) 0xC006000C))
#define R_UART0_STATUS		(*((volatile INT32U *) 0xC0060010))
#define R_UART0_FIFO		(*((volatile INT32U *) 0xC0060014))
#define R_UART0_TXDLY		(*((volatile INT32U *) 0xC0060018))
#define R_IRDA0_BUAD_RATE	(*((volatile INT32U *) 0xC006001C))
#define R_IRDA0_CTRL		(*((volatile INT32U *) 0xC0060020))
#define R_IRDA0_LOWPOWER	(*((volatile INT32U *) 0xC0060024))
#define P_UART1_BASE		((volatile INT32U *) 0xC0070000)
#define R_UART1_DATA		(*((volatile INT32U *) 0xC0070000))
#define R_UART1_RX_STATUS	(*((volatile INT32U *) 0xC0070004))
#define R_UART1_CTRL		(*((volatile INT32U *) 0xC0070008))
#define R_UART1_BAUD_RATE	(*((volatile INT32U *) 0xC007000C))
#define R_UART1_STATUS		(*((volatile INT32U *) 0xC0070010))
#define R_UART1_FIFO		(*((volatile INT32U *) 0xC0070014))
#define R_UART1_TXDLY		(*((volatile INT32U *) 0xC0070018))
#define R_IRDA1_BUAD_RATE	(*((volatile INT32U *) 0xC007001C))
#define R_IRDA1_CTRL		(*((volatile INT32U *) 0xC0070020))
#define R_IRDA1_LOWPOWER	(*((volatile INT32U *) 0xC0070024))

/******************************************************************************
 * Session: USB SFR
 * Layer: Driver Layer 1
 * Date: 2014/08/18
 * Note: USB SFR
 ******************************************************************************/
/******************************************************************************
 * USB: 0xD1100000
 ******************************************************************************/
#define VBUS_SAMPLE_PERIOD_MASK 0xFFFF

/* USB device register definitions */
#define UDC_BASE			(0xD1100000)
#define rUDC_EP12DMA		(*(volatile unsigned *) (UDC_BASE + 0x000))
#define rUDC_EP12DA			(*(volatile unsigned *) (UDC_BASE + 0x004))
#define rUDC_EP7DMA			(*(volatile unsigned *) (UDC_BASE + 0x008))
#define rUDC_EP7DA			(*(volatile unsigned *) (UDC_BASE + 0x00C))
#define rUDPHYI2CCR			(*(volatile unsigned *) (UDC_BASE + 0x020))
#define rUDPHYI2CDR			(*(volatile unsigned *) (UDC_BASE + 0x024))
#define rUDCCS_UDC			(*(volatile unsigned *) (UDC_BASE + 0x080))
#define rUDC_IRQ_ENABLE		(*(volatile unsigned *) (UDC_BASE + 0x084))
#define rUDC_IRQ_FLAG		(*(volatile unsigned *) (UDC_BASE + 0x088))
#define rUDC_IRQ_SOURCE		(*(volatile unsigned *) (UDC_BASE + 0x08c))
#define rEP4CS				(*(volatile unsigned *) (UDC_BASE + 0x100))
#define rEP4DC				(*(volatile unsigned *) (UDC_BASE + 0x104))
#define rEP4DP				(*(volatile unsigned *) (UDC_BASE + 0x108))
#define rEP4VB				(*(volatile unsigned *) (UDC_BASE + 0x10C))
#define rEP5CTL				(*(volatile unsigned *) (UDC_BASE + 0x140))
#define rEP5HDLEN			(*(volatile unsigned *) (UDC_BASE + 0x144))
#define rEP5FRAMCTL			(*(volatile unsigned *) (UDC_BASE + 0x148))
#define rEP5HDCTRL			(*(volatile unsigned *) (UDC_BASE + 0x14C))
#define rEP5EN				(*(volatile unsigned *) (UDC_BASE + 0x150))
#define rEP5RPTR			(*(volatile unsigned *) (UDC_BASE + 0x154))
#define rEP5WPTR			(*(volatile unsigned *) (UDC_BASE + 0x158))
#define rEP5FIFO			(*(volatile unsigned *) (UDC_BASE + 0x15C))
#define rEP5DMAEN			(*(volatile unsigned *) (UDC_BASE + 0x160))
#define rEP5VB				(*(volatile unsigned *) (UDC_BASE + 0x170))
#define rEPIFALTIF			(*(volatile unsigned *) (UDC_BASE + 0x174))
#define rEP6CS				(*(volatile unsigned *) (UDC_BASE + 0x180))
#define rEP6DC				(*(volatile unsigned *) (UDC_BASE + 0x184))
#define rEP6DP				(*(volatile unsigned *) (UDC_BASE + 0x188))
#define rEP6VB				(*(volatile unsigned *) (UDC_BASE + 0x18C))
#define rEP7CTL				(*(volatile unsigned *) (UDC_BASE + 0x1C0))
#define rEP7RPTR			(*(volatile unsigned *) (UDC_BASE + 0x1C4))
#define rEP7WPTR			(*(volatile unsigned *) (UDC_BASE + 0x1C8))
#define rEP7FIFO			(*(volatile unsigned *) (UDC_BASE + 0x1CC))
#define rEP7VB				(*(volatile unsigned *) (UDC_BASE + 0x1D0))
#define rDVIDEO_REFCLOCK	(*(volatile unsigned *) (UDC_BASE + 0x200))
#define rUDC_BIT_OP0		(*(volatile unsigned *) (UDC_BASE + 0x320))
#define rUDC_CP_CBW_TAG		(*(volatile unsigned *) (UDC_BASE + 0x328))
#define rEP12_CTRL			(*(volatile unsigned *) (UDC_BASE + 0x330))
#define rUDC_AS_CTRL		(*(volatile unsigned *) (UDC_BASE + 0x334))
#define rEP0_VB				(*(volatile unsigned *) (UDC_BASE + 0x340))
#define rEP0_SETUP_CTRL		(*(volatile unsigned *) (UDC_BASE + 0x344))
#define rEP0_SETUP_FIFO		(*(volatile unsigned *) (UDC_BASE + 0x348))
#define rEP0_CTRL			(*(volatile unsigned *) (UDC_BASE + 0x34C))
#define rEP0_CNTR			(*(volatile unsigned *) (UDC_BASE + 0x350))
#define rEP0_FIFO			(*(volatile unsigned *) (UDC_BASE + 0x354))
#define rEP1S_CTRL			(*(volatile unsigned *) (UDC_BASE + 0x358))
#define rEP1S_FIFO			(*(volatile unsigned *) (UDC_BASE + 0x35C))
#define rEP12_STATUS		(*(volatile unsigned *) (UDC_BASE + 0x364))
#define rEP12_CNTRL			(*(volatile unsigned *) (UDC_BASE + 0x368))
#define rEP12_CNTRH			(*(volatile unsigned *) (UDC_BASE + 0x36C))
#define rEP12_PIPO			(*(volatile unsigned *) (UDC_BASE + 0x370))
#define rEP3CS				(*(volatile unsigned *) (UDC_BASE + 0x374))
#define rEP3DC				(*(volatile unsigned *) (UDC_BASE + 0x378))
#define rEP3DP				(*(volatile unsigned *) (UDC_BASE + 0x37C))
#define rEP3VB				(*(volatile unsigned *) (UDC_BASE + 0x380))
#define rEP0_OUT_NAK		(*(volatile unsigned *) (UDC_BASE + 0x384))
#define rEP0_IN_NAK			(*(volatile unsigned *) (UDC_BASE + 0x388))
#define rEP1_NAK			(*(volatile unsigned *) (UDC_BASE + 0x38C))
#define rEP2_NAK			(*(volatile unsigned *) (UDC_BASE + 0x390))
#define rEP12_VB			(*(volatile unsigned *) (UDC_BASE + 0x398))
#define rEP12_POCNTL		(*(volatile unsigned *) (UDC_BASE + 0x39C))
#define rEP12_POCNTH		(*(volatile unsigned *) (UDC_BASE + 0x3A0))
#define rUDLC_SET0			(*(volatile unsigned *) (UDC_BASE + 0x3B0))
#define rUDLC_SET1			(*(volatile unsigned *) (UDC_BASE + 0x3B4))
#define rUDC_STATUS			(*(volatile unsigned *) (UDC_BASE + 0x3B8))
#define rUDC_STALL_CTRL		(*(volatile unsigned *) (UDC_BASE + 0x3BC))
#define rUDLC_SET2			(*(volatile unsigned *) (UDC_BASE + 0x3C0))
#define rUDC_LCS2			(*(volatile unsigned *) (UDC_BASE + 0x3C4))
#define rUDC_LCS3			(*(volatile unsigned *) (UDC_BASE + 0x3C8))
#define rUDC_ADDR			(*(volatile unsigned *) (UDC_BASE + 0x3F4))
#define rDLCIF_UDLC			(*(volatile unsigned *) (UDC_BASE + 0x400))
#define rDLCIE_UDLC			(*(volatile unsigned *) (UDC_BASE + 0x404))
#define rDLCIS_UDC			(*(volatile unsigned *) (UDC_BASE + 0x408))
#define rSTANDARD_REQ_IF	(*(volatile unsigned *) (UDC_BASE + 0x410))
#define rSTANDARD_REQ_IE	(*(volatile unsigned *) (UDC_BASE + 0x414))

/* New register definition for EP89 AB */
#define rEP89_DMA		(*(volatile unsigned *) (UDC_BASE + 0x010))
#define rEP89_DA		(*(volatile unsigned *) (UDC_BASE + 0x014))
#define rEPAB_DMA		(*(volatile unsigned *) (UDC_BASE + 0x018))
#define rEPAB_DA		(*(volatile unsigned *) (UDC_BASE + 0x01C))
#define rNEWEP_IF		(*(volatile unsigned *) (UDC_BASE + 0x420))
#define rNEWEP_IE		(*(volatile unsigned *) (UDC_BASE + 0x424))
#define rEP89_CTRL		(*(volatile unsigned *) (UDC_BASE + 0x500))
#define rEP89_PPC		(*(volatile unsigned *) (UDC_BASE + 0x504))
#define rEP89_FS		(*(volatile unsigned *) (UDC_BASE + 0x508))
#define rEP89_PICL		(*(volatile unsigned *) (UDC_BASE + 0x50C))
#define rEP89_PICH		(*(volatile unsigned *) (UDC_BASE + 0x510))
#define rEP89_POCL		(*(volatile unsigned *) (UDC_BASE + 0x514))
#define rEP89_POCH		(*(volatile unsigned *) (UDC_BASE + 0x518))
#define rEP89_FIFO		(*(volatile unsigned *) (UDC_BASE + 0x51C))
#define rEP89_VB		(*(volatile unsigned *) (UDC_BASE + 0x520))
#define rEP89_SETTING	(*(volatile unsigned *) (UDC_BASE + 0x52C))
#define rEPAB_CTRL		(*(volatile unsigned *) (UDC_BASE + 0x550))
#define rEPAB_PPC		(*(volatile unsigned *) (UDC_BASE + 0x554))
#define rEPAB_FS		(*(volatile unsigned *) (UDC_BASE + 0x558))
#define rEPAB_PICL		(*(volatile unsigned *) (UDC_BASE + 0x55C))
#define rEPAB_PICH		(*(volatile unsigned *) (UDC_BASE + 0x560))
#define rEPAB_POCL		(*(volatile unsigned *) (UDC_BASE + 0x564))
#define rEPAB_POCH		(*(volatile unsigned *) (UDC_BASE + 0x568))
#define rEPAB_FIFO		(*(volatile unsigned *) (UDC_BASE + 0x56C))
#define rEPAB_VB		(*(volatile unsigned *) (UDC_BASE + 0x570))
#define rEPAB_SETTING	(*(volatile unsigned *) (UDC_BASE + 0x57C))

/* New registers added in GP22 */
#define rEPINF_SETTING	(*(volatile unsigned *) (UDC_BASE + 0x028))
#define rEPC_EVENT		(*(volatile unsigned *) (UDC_BASE + 0x580))
#define rEPC_CTRL		(*(volatile unsigned *) (UDC_BASE + 0x584))
#define rEPC_WRC		(*(volatile unsigned *) (UDC_BASE + 0x588))
#define rEPC_FUN		(*(volatile unsigned *) (UDC_BASE + 0x58C))
#define rEPC_DATA		(*(volatile unsigned *) (UDC_BASE + 0x590))

//==========================================================
#define rSYS_CTRL_NEW	(*(volatile unsigned *) (0xD0000000 + 0x08))

/******************************************************************************
 * USB HOST
 ******************************************************************************/
#define USBH_BASE	0xD0C00000
#define R_USBH_CONTROL					(*(volatile INT32U *) (USBH_BASE + 0x04))
#define R_USBH_EHCI_ISOIN_CTRL			(*(volatile INT32U *) (USBH_BASE + 0x180))
#define R_USBH_EHCI_ISOIN_INIT_SADDR_A	(*(volatile INT32U *) (USBH_BASE + 0x184))
#define R_USBH_EHCI_ISOIN_INIT_SADDR_B	(*(volatile INT32U *) (USBH_BASE + 0x188))
#define R_USBH_EHCI_ISOIN_HW_ADDR_A		(*(volatile INT32U *) (USBH_BASE + 0x18C))
#define R_USBH_EHCI_ISOIN_HW_ADDR_B		(*(volatile INT32U *) (USBH_BASE + 0x190))
#define R_USBH_EHCI_ISOIN_INTEN			(*(volatile INT32U *) (USBH_BASE + 0x194))
#define R_USBH_EHCI_ISOIN_INT			(*(volatile INT32U *) (USBH_BASE + 0x198))
#define R_USBH_EHCI_ISOIN_BUFBOUND		(*(volatile INT32U *) (USBH_BASE + 0x19C))
#define R_USBH_EHCI_ISOIN_HEADER0		(*(volatile INT32U *) (USBH_BASE + 0x1A0))
#define R_USBH_EHCI_ISOIN_HEADER1		(*(volatile INT32U *) (USBH_BASE + 0x1A4))
#define R_USBH_EHCI_ISOIN_HEADER2		(*(volatile INT32U *) (USBH_BASE + 0x1A8))

#define R_USBH_OHCI_ISOIN_CTRL			(*(volatile INT32U *) (USBH_BASE + 0x1C0))
#define R_USBH_OHCI_ISOIN_INIT_SADDR_A	(*(volatile INT32U *) (USBH_BASE + 0x1C4))
#define R_USBH_OHCI_ISOIN_INIT_SADDR_B	(*(volatile INT32U *) (USBH_BASE + 0x1C8))
#define R_USBH_OHCI_ISOIN_HW_ADDR_A		(*(volatile INT32U *) (USBH_BASE + 0x1CC))
#define R_USBH_OHCI_ISOIN_HW_ADDR_B		(*(volatile INT32U *) (USBH_BASE + 0x1D0))
#define R_USBH_OHCI_ISOIN_INTEN			(*(volatile INT32U *) (USBH_BASE + 0x1D4))
#define R_USBH_OHCI_ISOIN_INT			(*(volatile INT32U *) (USBH_BASE + 0x1D8))
#define R_USBH_OHCI_ISOIN_BUFBOUND		(*(volatile INT32U *) (USBH_BASE + 0x1DC))
#define R_USBH_OHCI_ISOIN_HEADER0		(*(volatile INT32U *) (USBH_BASE + 0x1E0))
#define R_USBH_OHCI_ISOIN_HEADER1		(*(volatile INT32U *) (USBH_BASE + 0x1E4))
#define R_USBH_OHCI_ISOIN_HEADER2		(*(volatile INT32U *) (USBH_BASE + 0x1E8))

/******************************************************************************
 * Session: SPI SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: SPI SFR
 ******************************************************************************/
/******************************************************************************
 * SPI: 0xC0080000
 ******************************************************************************/
#define SPI0_BASE						0xC0090000
#define P_SPI0_CTRL						((volatile INT32U *) (SPI0_BASE + 0x00))
#define P_SPI0_TX_DATA					((volatile INT32U *) (SPI0_BASE + 0x08))
#define P_SPI0_RX_DATA					((volatile INT32U *) (SPI0_BASE + 0x10))

#define R_SPI0_CTRL						(*((volatile INT32U *) (SPI0_BASE + 0x00)))
#define R_SPI0_TX_STATUS				(*((volatile INT32U *) (SPI0_BASE + 0x04)))
#define R_SPI0_TX_DATA					(*((volatile INT32U *) (SPI0_BASE + 0x08)))
#define R_SPI0_RX_STATUS				(*((volatile INT32U *) (SPI0_BASE + 0x0C)))
#define R_SPI0_RX_DATA					(*((volatile INT32U *) (SPI0_BASE + 0x10)))
#define R_SPI0_MISC						(*((volatile INT32U *) (SPI0_BASE + 0x14)))
#define R_SPI0_DMA_RX_CYC				(*((volatile INT32U *) (SPI0_BASE + 0x1C)))		//for SPI RX without Tx
#define SPI1_BASE						0xC00A0000
#define P_SPI1_CTRL						((volatile INT32U *) (SPI1_BASE + 0x00))
#define P_SPI1_TX_DATA					((volatile INT32U *) (SPI1_BASE + 0x08))
#define P_SPI1_RX_DATA					((volatile INT32U *) (SPI1_BASE + 0x10))

#define R_SPI1_CTRL						(*((volatile INT32U *) (SPI1_BASE + 0x00)))
#define R_SPI1_TX_STATUS				(*((volatile INT32U *) (SPI1_BASE + 0x04)))
#define R_SPI1_TX_DATA					(*((volatile INT32U *) (SPI1_BASE + 0x08)))
#define R_SPI1_RX_STATUS				(*((volatile INT32U *) (SPI1_BASE + 0x0C)))
#define R_SPI1_RX_DATA					(*((volatile INT32U *) (SPI1_BASE + 0x10)))
#define R_SPI1_MISC						(*((volatile INT32U *) (SPI1_BASE + 0x14)))
#define R_SPI1_DMA_RX_CYC				(*((volatile INT32U *) (SPI1_BASE + 0x1C)))		//for SPI RX without Tx
/******************************************************************************
 * RTC: 0xC0050000
 ******************************************************************************/
#define EXT_RTC_BASE	((volatile INT32U *) 0xC0050000)

/******************************************************************************
 * Session: SDC SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: SDC SFR
 ******************************************************************************/
/******************************************************************************
 * SDC: 0xC0250000
 ******************************************************************************/
#define P_SDC0_BASE			0xC0250000
#define P_SDC0_DATA_TX		((volatile INT32U *) (P_SDC0_BASE + 0x0000))
#define P_SDC0_DATA_RX		((volatile INT32U *) (P_SDC0_BASE + 0x0004))
#define R_SDC0_DATA_TX		(*((volatile INT32U *) (P_SDC0_BASE + 0x0000)))
#define R_SDC0_DATA_RX		(*((volatile INT32U *) (P_SDC0_BASE + 0x0004)))
#define R_SDC0_CMMAND		(*((volatile INT32U *) (P_SDC0_BASE + 0x0008)))
#define R_SDC0_ARGUMENT		(*((volatile INT32U *) (P_SDC0_BASE + 0x000C)))
#define R_SDC0_RESPONSE		(*((volatile INT32U *) (P_SDC0_BASE + 0x0010)))
#define R_SDC0_STATUS		(*((volatile INT32U *) (P_SDC0_BASE + 0x0014)))
#define R_SDC0_CTRL			(*((volatile INT32U *) (P_SDC0_BASE + 0x0018)))
#define R_SDC0_INTEN		(*((volatile INT32U *) (P_SDC0_BASE + 0x001C)))
#define R_SDC0_CLKGATE		(*((volatile INT32U *) (P_SDC0_BASE + 0x0020)))
#define R_SDC0_TimeOutEN	(*((volatile INT32U *) (P_SDC0_BASE + 0x0024)))
#define R_SDC0_TimeOut_THD	(*((volatile INT32U *) (P_SDC0_BASE + 0x0028)))


/******************************************************************************
 * SDC1: 0xD1200000
 ******************************************************************************/
#define P_SDC1_BASE			0xC0260000
#define P_SDC1_DATA_TX		((volatile INT32U *) (P_SDC1_BASE + 0x0000))
#define P_SDC1_DATA_RX		((volatile INT32U *) (P_SDC1_BASE + 0x0004))
#define R_SDC1_DATA_TX		(*((volatile INT32U *) (P_SDC1_BASE + 0x0000)))
#define R_SDC1_DATA_RX		(*((volatile INT32U *) (P_SDC1_BASE + 0x0004)))
#define R_SDC1_CMMAND		(*((volatile INT32U *) (P_SDC1_BASE + 0x0008)))
#define R_SDC1_ARGUMENT		(*((volatile INT32U *) (P_SDC1_BASE + 0x000C)))
#define R_SDC1_RESPONSE		(*((volatile INT32U *) (P_SDC1_BASE + 0x0010)))
#define R_SDC1_STATUS		(*((volatile INT32U *) (P_SDC1_BASE + 0x0014)))
#define R_SDC1_CTRL			(*((volatile INT32U *) (P_SDC1_BASE + 0x0018)))
#define R_SDC1_INTEN		(*((volatile INT32U *) (P_SDC1_BASE + 0x001C)))
#define R_SDC1_CLKGATE		(*((volatile INT32U *) (P_SDC1_BASE + 0x0020)))
#define R_SDC1_TimeOutEN	(*((volatile INT32U *) (P_SDC1_BASE + 0x0024)))
#define R_SDC1_TimeOut_THD	(*((volatile INT32U *) (P_SDC1_BASE + 0x0028)))



/******************************************************************************
 * Session: ADC SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: ADC SFR
 ******************************************************************************/
/******************************************************************************
 * ADC: 0xC00D0000
 ******************************************************************************/
#define P_ADC_ASADC_DATA	((volatile INT32U *) 0xC00D0010)
#define P_ADC_MADC_DATA		((volatile INT32U *) 0xC00D0008)
#define R_ADC_SETUP			(*((volatile INT32U *) 0xC00D0000))
#define R_ADC_MADC_CTRL		(*((volatile INT32U *) 0xC00D0004))
#define R_ADC_MADC_DATA		(*((volatile INT32U *) 0xC00D0008))
#define R_ADC_ASADC_CTRL	(*((volatile INT32U *) 0xC00D000C))
#define R_ADC_ASADC_DATA	(*((volatile INT32U *) 0xC00D0010))
#define R_ADC_SH_WAIT		(*((volatile INT32U *) 0xC00D001C))
#define R_ADC_TP_CTRL		(*((volatile INT32U *) 0xC00C0014))
#define R_ADC_USELINEIN		(*((volatile INT32U *) 0xC00D0018))
#define R_ADC_PGA_GAIN		(*((volatile INT32U *) 0xC00C006C))
#define R_MIC_ASADC_CTRL	(*((volatile INT32U *) 0xC00C004C))
#define R_MIC_ASADC_DATA	(*((volatile INT32U *) 0xC00C0050))
#define R_MIC_READY			(*((volatile INT32U *) 0xC00C0044))

/******************************************************************************
 * Session: DAC SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: DAC SFR
 ******************************************************************************/
/******************************************************************************
 * DAC: 0xC00D0000
 ******************************************************************************/
#define P_DAC_CHA_DATA	((volatile INT32U *) 0xC00E0004)
#define P_DAC_CHB_DATA	((volatile INT32U *) 0xC00E0024)
#define R_DAC_CHA_CTRL	(*((volatile INT32U *) 0xC00E0000))
#define R_DAC_CHA_DATA	(*((volatile INT32U *) 0xC00E0004))
#define R_DAC_CHA_FIFO	(*((volatile INT32U *) 0xC00E0008))
#define R_DAC_CHB_CTRL	(*((volatile INT32U *) 0xC00E0020))
#define R_DAC_CHB_DATA	(*((volatile INT32U *) 0xC00E0024))
#define R_DAC_CHB_FIFO	(*((volatile INT32U *) 0xC00E0028))
#define R_DAC_PGA		(*((volatile INT32U *) 0xC00E002C))
#define R_DAC_FILTER	(*((volatile INT32U *) 0xC00E003C))

/******************************************************************************
 * Session: System control SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: System control SFR
 ******************************************************************************/
/******************************************************************************
 * System control: 0xD0000000
 ******************************************************************************/
#define R_SYSTEM_BODY_ID		(*((volatile INT32U *) 0xD0000000))
#define R_SYSTEM_MISC_CTRL0		(*((volatile INT32U *) 0xD0000008))
#define R_SYSTEM_CTRL			(*((volatile INT32U *) 0xD000000C))
#define R_SYSTEM_CLK_EN0		(*((volatile INT32U *) 0xD0000010))
#define R_SYSTEM_CLK_EN1		(*((volatile INT32U *) 0xD0000014))
#define R_SYSTEM_RESET_FLAG		(*((volatile INT32U *) 0xD0000018))
#define R_SYSTEM_CLK_CTRL		(*((volatile INT32U *) 0xD000001C))
#define R_SYSTEM_LVR_CTRL		(*((volatile INT32U *) 0xD0000020))
#define R_SYSTEM_WATCHDOG_CTRL	(*((volatile INT32U *) 0xD0000028))
#define R_SYSTEM_WATCHDOG_CLEAR (*((volatile INT32U *) 0xD000002C))
#define R_SYSTEM_WAIT			(*((volatile INT32U *) 0xD0000030))
#define R_SYSTEM_HALT			(*((volatile INT32U *) 0xD0000034))
#define R_SYSTEM_SLEEP			(*((volatile INT32U *) 0xD0000038))
#define R_SYSTEM_POWER_STATE	(*((volatile INT32U *) 0xD000003C))
#define R_SYSTEM_MISC_CTRL1		(*((volatile INT32U *) 0xD0000044))
#define R_SYSTEM_MIPI_CTRL_CLK	(*((volatile INT32U *) 0xD0000048))
#define R_SYSTEM_CHR_CTRL		(*((volatile INT32U *) 0xD000004C))
#define R_SYSTEM_POWER_CTRL2	(*((volatile INT32U *) 0xD0000050))
#define R_SYSTEM_CKGEN_CTRL		(*((volatile INT32U *) 0xD0000058))
#define R_SYSTEM_PLLEN			(*((volatile INT32U *) 0xD000005C))
#define R_SYSTEM_PLL_WAIT_CLK	(*((volatile INT32U *) 0xD0000060))
#define R_SYSTEM_MISC_CTRL2		(*((volatile INT32U *) 0xD0000060))
#define R_SYSTEM_POWER_CTRL0	(*((volatile INT32U *) 0xD0000064))
#define R_SYSTEM_POWER_CTRL1	(*((volatile INT32U *) 0xD0000068))
#define R_SYSTEM_CODEC_CTRL0	(*((volatile INT32U *) 0xD000006C))
#define R_SYSTEM_CODEC_CTRL1	(*((volatile INT32U *) 0xD0000070))
#define R_SYSTEM_MISC_CTRL4		(*((volatile INT32U *) 0xD0000074))
#define R_SYSTEM_HDMI_CTRL		(*((volatile INT32U *) 0xD0000078))
#define R_SYSTEM_CPUCLK_CTRL	(*((volatile INT32U *) 0xD000007C))
#define R_SYSTEM_MISC_CTRL5		(*((volatile INT32U *) 0xD0000084))
#define R_SYSTEM_WATCHDOG_CTRL_WP1	(*((volatile INT32U *) 0xD0000088))
#define R_SYSTEM_WATCHDOG_CTRL_WP2	(*((volatile INT32U *) 0xD000008C))
#define R_SYSTEM_DDR_LDO		(*((volatile INT32U *) 0xD00000AC))
#define R_SYSTEM_APLL_FREQ		(*((volatile INT32U *) 0xD00000C4))
#define R_SYSTEM_CLK_EN2		(*((volatile INT32U *) 0xD00000E0))

/******************************************************************************
 * Session: CONV420TO422 SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: CONV420TO422 SFR
 ******************************************************************************/
#define P_CONV420_B_BASE	((volatile INT32U *) 0xC01B0000)
#define P_CONV420_A_BASE	((volatile INT32U *) 0xC01C0000)

/******************************************************************************
 * Session: Interrupt control SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Interrupt control SFR
 ******************************************************************************/
/******************************************************************************
 * Interrupt control: 0xD0100000
 ******************************************************************************/
#define P_INTERRUPT_BASE			(0xD0100000)
#define P_EXTERNAL_INT_BASE			(0xD0100020)

#define R_INT_IRQFLAG				(*((volatile INT32U *) 0xD0100000))
#define R_INT_FIQFLAG				(*((volatile INT32U *) 0xD0100004))
#define R_INT_I_PMST				(*((volatile INT32U *) 0xD0100008))
#define R_INT_I_PSLV0				(*((volatile INT32U *) 0xD0100010))
#define R_INT_I_PSLV1				(*((volatile INT32U *) 0xD0100014))
#define R_INT_I_PSLV2				(*((volatile INT32U *) 0xD0100018))
#define R_INT_I_PSLV3				(*((volatile INT32U *) 0xD010001C))
#define R_INT_KECON					(*((volatile INT32U *) 0xD0100020))
#define R_INT_KEYCH					(*((volatile INT32U *) 0xD0100024))
#define R_INT_IRQNUM				(*((volatile INT32U *) 0xD0100028))
#define R_INT_FIQNUM				(*((volatile INT32U *) 0xD010002C))
#define R_INT_IRQMASK_LO			(*((volatile INT32U *) 0xD0100030))
#define R_INT_FIQMASK				(*((volatile INT32U *) 0xD0100034))
#define R_INT_GMASK					(*((volatile INT32U *) 0xD0100038))
#define R_INT_FIQMASK2				(*((volatile INT32U *) 0xD010003C))
#define R_INT_IRQMASK_HI			(*((volatile INT32U *) 0xD0100054))

/******************************************************************************
 * Session: Memory control SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Memory control SFR
 ******************************************************************************/
/******************************************************************************
 * Memory control: 0xD0200000 and D09001F0
 ******************************************************************************/
#define R_MEM_CS0_CTRL				(*((volatile INT32U *) 0xD0200000))
#define R_MEM_CS1_CTRL				(*((volatile INT32U *) 0xD0200004))
#define R_MEM_CS2_CTRL				(*((volatile INT32U *) 0xD0200008))
#define R_MEM_CS3_CTRL				(*((volatile INT32U *) 0xD020000C))
#define R_MEM_SDRAM_CTRL0			(*((volatile INT32U *) 0xD0200040))
#define R_MEM_SDRAM_CTRL1			(*((volatile INT32U *) 0xD0200044))
#define R_MEM_SDRAM_TIMING			(*((volatile INT32U *) 0xD0200048))
#define R_MEM_SDRAM_CBRCYC			(*((volatile INT32U *) 0xD020004C))
#define R_MEM_SDRAM_MISC			(*((volatile INT32U *) 0xD0200050))
#define R_MEM_SDRAM_STATUS			(*((volatile INT32U *) 0xD0200054))
#define R_MEM_NOR_FLASH_ADDR		(*((volatile INT32U *) 0xD0200024))
#define R_MEM_IO_CTRL				(*((volatile INT32U *) 0xD0200060))
#define R_MEM_BUS_ARBITER_BASE		((volatile INT32U *) 0xD0200080)
#define R_MEM_BUS_MONITOR_EN		(*((volatile INT32U *) 0xD09001F0))
#define R_MEM_BUS_MONITOR_PERIOD	(*((volatile INT32U *) 0xD09001F4))
#define R_MEM_SDRAM_IDLE_RATE		(*((volatile INT32U *) 0xD09001F8))
#define R_MEM_M0_UTILIZATION		(*((volatile INT32U *) 0xD0900100))
#define R_MEM_M1_UTILIZATION		(*((volatile INT32U *) 0xD0900104))
#define R_MEM_M2_UTILIZATION		(*((volatile INT32U *) 0xD0900108))
#define R_MEM_M3_UTILIZATION		(*((volatile INT32U *) 0xD090010C))
#define R_MEM_M4_UTILIZATION		(*((volatile INT32U *) 0xD0900110))
#define R_MEM_M5_UTILIZATION		(*((volatile INT32U *) 0xD0900114))
#define R_MEM_M6_UTILIZATION		(*((volatile INT32U *) 0xD0900118))
#define R_MEM_M7_UTILIZATION		(*((volatile INT32U *) 0xD090011C))
#define R_MEM_M8_UTILIZATION		(*((volatile INT32U *) 0xD0900120))
#define R_MEM_M9_UTILIZATION		(*((volatile INT32U *) 0xD0900124))
#define R_MEM_M10_UTILIZATION		(*((volatile INT32U *) 0xD0900128))
#define R_MEM_M11_UTILIZATION		(*((volatile INT32U *) 0xD090012C))
#define R_MEM_M0_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900130))
#define R_MEM_M1_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900134))
#define R_MEM_M2_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900138))
#define R_MEM_M3_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD090013C))
#define R_MEM_M4_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900140))
#define R_MEM_M5_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900144))
#define R_MEM_M6_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900148))
#define R_MEM_M7_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD090014C))
#define R_MEM_M8_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900150))
#define R_MEM_M9_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900154))
#define R_MEM_M10_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD0900158))
#define R_MEM_M11_UTILIZATION_BYTE	(*((volatile INT32U *) 0xD090015C))

/******************************************************************************
 * Session: Bus Arbiter SFR
 * Layer: Driver Layer 1
 * Date: 2016/02/19
 * Note: Bus Arbiter SFR
 ******************************************************************************/
/******************************************************************************
 * Bus Arbiter: 0xD0200080
 ******************************************************************************/
#define R_BUS_ARB_MB2SCAN		(*((volatile INT32U *) 0xD0200080))
#define R_BUS_ARB_CONV420TO422	(*((volatile INT32U *) 0xD0200084))
#define R_BUS_ARB_HDMI			(*((volatile INT32U *) 0xD0200088))
#define R_BUS_ARB_SCA_BP		(*((volatile INT32U *) 0xD020008C))
#define R_BUS_ARB_PSCA			(*((volatile INT32U *) 0xD0200090))
#define R_BUS_ARB_PSCA_B		(*((volatile INT32U *) 0xD0200094))
#define R_BUS_ARB_SPU			(*((volatile INT32U *) 0xD0200098))
#define R_BUS_ARB_PPUPPU		(*((volatile INT32U *) 0xD020009C))
#define R_BUS_ARB_H264_SCA		(*((volatile INT32U *) 0xD02000A0))
#define R_BUS_ARB_H264			(*((volatile INT32U *) 0xD02000A4))
#define R_BUS_ARB_JPG			(*((volatile INT32U *) 0xD02000A8))
#define R_BUS_ARB_USB20			(*((volatile INT32U *) 0xD02000AC))
#define R_BUS_ARB_USB20HOST		(*((volatile INT32U *) 0xD02000B0))
#define R_BUS_ARB_PSCA_MB		(*((volatile INT32U *) 0xD02000B4))
#define R_BUS_ARB_PSCA_MB_B		(*((volatile INT32U *) 0xD02000B8))
#define R_BUS_ARB_SCAL			(*((volatile INT32U *) 0xD02000BC))
#define R_BUS_ARB_FFT			(*((volatile INT32U *) 0xD02000C0))
#define R_BUS_ARB_FD			(*((volatile INT32U *) 0xD02000C4))
#define R_BUS_ARB_SPIFC			(*((volatile INT32U *) 0xD02000C8))
#define R_BUS_ARB_PPU			(*((volatile INT32U *) 0xD02000CC))
#define R_BUS_ARB_ROT			(*((volatile INT32U *) 0xD02000D0))
#define R_BUS_ARB_NFC			(*((volatile INT32U *) 0xD02000D4))
#define R_BUS_ARB_CDSP_R		(*((volatile INT32U *) 0xD02000D8))
#define R_BUS_ARB_DMA			(*((volatile INT32U *) 0xD02000DC))
#define R_BUS_ARB_ARM			(*((volatile INT32U *) 0xD02000E0))
#define R_BUS_ARB_ARM_NC		(*((volatile INT32U *) 0xD02000E4))
#define R_BUS_ARB_MP3			(*((volatile INT32U *) 0xD02000E8))
#define R_BUS_ARB_SD30			(*((volatile INT32U *) 0xD02000EC))
#define R_BUS_ARB_RESERVED0		(*((volatile INT32U *) 0xD02000F0))
#define R_BUS_ARB_RESERVED1		(*((volatile INT32U *) 0xD02000F4))

/******************************************************************************
 * Session: DDR controller SFR
 * Layer: Driver Layer 1
 * Date: 2016/07/06
 * Note: DDR controller SFR
 ******************************************************************************/
#define R_DDR_CTRL	(*((volatile INT32U *) 0xD0200310))
#define R_DDR_CMD	(*((volatile INT32U *) 0xD0203004))

/******************************************************************************
 * Session: DMA controller SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: DMA controller SFR
 ******************************************************************************/
/******************************************************************************
 * DMA controller: 0xD0300000
 ******************************************************************************/
#define R_DMA0_CTRL			(*((volatile INT32U *) 0xD0300000))
#define R_DMA0_SRC_ADDR		(*((volatile INT32U *) 0xD0300004))
#define R_DMA0_TAR_ADDR		(*((volatile INT32U *) 0xD0300008))
#define R_DMA0_TX_COUNT		(*((volatile INT32U *) 0xD030000C))
#define R_DMA0_SPRITE_SIZE	(*((volatile INT32U *) 0xD0300010))
#define R_DMA0_TRANSPARENT	(*((volatile INT32U *) 0xD0300014))
#define R_DMA0_MISC			(*((volatile INT32U *) 0xD0300018))
#define R_DMA1_CTRL			(*((volatile INT32U *) 0xD0300040))
#define R_DMA1_SRC_ADDR		(*((volatile INT32U *) 0xD0300044))
#define R_DMA1_TAR_ADDR		(*((volatile INT32U *) 0xD0300048))
#define R_DMA1_TX_COUNT		(*((volatile INT32U *) 0xD030004C))
#define R_DMA1_SPRITE_SIZE	(*((volatile INT32U *) 0xD0300050))
#define R_DMA1_TRANSPARENT	(*((volatile INT32U *) 0xD0300054))
#define R_DMA1_MISC			(*((volatile INT32U *) 0xD0300058))
#define R_DMA2_CTRL			(*((volatile INT32U *) 0xD0300080))
#define R_DMA2_SRC_ADDR		(*((volatile INT32U *) 0xD0300084))
#define R_DMA2_TAR_ADDR		(*((volatile INT32U *) 0xD0300088))
#define R_DMA2_TX_COUNT		(*((volatile INT32U *) 0xD030008C))
#define R_DMA2_SPRITE_SIZE	(*((volatile INT32U *) 0xD0300090))
#define R_DMA2_TRANSPARENT	(*((volatile INT32U *) 0xD0300094))
#define R_DMA2_MISC			(*((volatile INT32U *) 0xD0300098))
#define R_AES_LOAD_KEY		(*((volatile INT32U *) 0xD030009C))
#define R_AES_KEY0			(*((volatile INT32U *) 0xD03000A0))
#define R_AES_KEY1			(*((volatile INT32U *) 0xD03000A4))
#define R_AES_KEY2			(*((volatile INT32U *) 0xD03000A8))
#define R_AES_KEY3			(*((volatile INT32U *) 0xD03000AC))
#define R_DES_CTRL			(*((volatile INT32U *) 0xD0300220))
#define R_DES_KEY0_LSB		(*((volatile INT32U *) 0xD0300224))
#define R_DES_KEY0_MSB		(*((volatile INT32U *) 0xD0300228))
#define R_DES_KEY1_LSB		(*((volatile INT32U *) 0xD030022C))
#define R_DES_KEY1_MSB		(*((volatile INT32U *) 0xD0300230))
#define R_DES_KEY2_LSB		(*((volatile INT32U *) 0xD0300234))
#define R_DES_KEY2_MSB		(*((volatile INT32U *) 0xD0300238))
#define R_AES_REV			(*((volatile INT32U *) 0xD03000B8))
#define R_DES_IV_LSB		(*((volatile INT32U *) 0xD03000E0))
#define R_DES_IV_MSB		(*((volatile INT32U *) 0xD03000E4))
#define R_AES_IV_0			(*((volatile INT32U *) 0xD03000E8))
#define R_AES_IV_1			(*((volatile INT32U *) 0xD03000EC))
#define R_AES_IV_2			(*((volatile INT32U *) 0xD03000F0))
#define R_AES_IV_3			(*((volatile INT32U *) 0xD03000F4))
#define R_DMA3_CTRL			(*((volatile INT32U *) 0xD03000C0))
#define R_DMA3_SRC_ADDR		(*((volatile INT32U *) 0xD03000C4))
#define R_DMA3_TAR_ADDR		(*((volatile INT32U *) 0xD03000C8))
#define R_DMA3_TX_COUNT		(*((volatile INT32U *) 0xD03000CC))
#define R_DMA3_SPRITE_SIZE	(*((volatile INT32U *) 0xD03000D0))
#define R_DMA3_TRANSPARENT	(*((volatile INT32U *) 0xD03000D4))
#define R_DMA3_MISC			(*((volatile INT32U *) 0xD03000D8))
#define R_DMA_LINE_LEN		(*((volatile INT32U *) 0xD03001F0))
#define R_DMA_DEVICE		(*((volatile INT32U *) 0xD03001F4))
#define R_DMA_CEMODE		(*((volatile INT32U *) 0xD03001F8))
#define R_DMA_INT			(*((volatile INT32U *) 0xD03001FC))
#define R_DMA4_CTRL			(*((volatile INT32U *) 0xD0300200))
#define R_DMA4_SRC_ADDR		(*((volatile INT32U *) 0xD0300204))
#define R_DMA4_TAR_ADDR		(*((volatile INT32U *) 0xD0300208))
#define R_DMA4_TX_COUNT		(*((volatile INT32U *) 0xD030020C))
#define R_DMA4_SPRITE_SIZE	(*((volatile INT32U *) 0xD0300210))
#define R_DMA4_TRANSPARENT	(*((volatile INT32U *) 0xD0300214))
#define R_DMA4_MISC			(*((volatile INT32U *) 0xD0300218))
#define R_DMA5_CTRL			(*((volatile INT32U *) 0xD0300240))
#define R_DMA5_SRC_ADDR		(*((volatile INT32U *) 0xD0300244))
#define R_DMA5_TAR_ADDR		(*((volatile INT32U *) 0xD0300248))
#define R_DMA5_TX_COUNT		(*((volatile INT32U *) 0xD030024C))
#define R_DMA5_SPRITE_SIZE	(*((volatile INT32U *) 0xD0300250))
#define R_DMA5_TRANSPARENT	(*((volatile INT32U *) 0xD0300254))
#define R_DMA5_MISC			(*((volatile INT32U *) 0xD0300258))
#define R_DMA6_CTRL			(*((volatile INT32U *) 0xD0300280))
#define R_DMA6_SRC_ADDR		(*((volatile INT32U *) 0xD0300284))
#define R_DMA6_TAR_ADDR		(*((volatile INT32U *) 0xD0300288))
#define R_DMA6_TX_COUNT		(*((volatile INT32U *) 0xD030028C))
#define R_DMA6_SPRITE_SIZE	(*((volatile INT32U *) 0xD0300290))
#define R_DMA6_TRANSPARENT	(*((volatile INT32U *) 0xD0300294))
#define R_DMA6_MISC			(*((volatile INT32U *) 0xD0300298))
#define R_DMA7_CTRL			(*((volatile INT32U *) 0xD03002C0))
#define R_DMA7_SRC_ADDR		(*((volatile INT32U *) 0xD03002C4))
#define R_DMA7_TAR_ADDR		(*((volatile INT32U *) 0xD03002C8))
#define R_DMA7_TX_COUNT		(*((volatile INT32U *) 0xD03002CC))
#define R_DMA7_SPRITE_SIZE	(*((volatile INT32U *) 0xD03002D0))
#define R_DMA7_TRANSPARENT	(*((volatile INT32U *) 0xD03002D4))
#define R_DMA7_MISC			(*((volatile INT32U *) 0xD03002D8))

/******************************************************************************
 * Session: PPU/TFT/STN/TVE/CSI controller SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: PPU/TFT/STN/TVE/CSI controller SFR
 ******************************************************************************/
/******************************************************************************
 * PICTURE PROCESS UNIT(PPU) CONTROL REGISTERS
 ******************************************************************************/
#define R_PPU_PALETTE_CTRL		(*((volatile INT32U *) 0xD05000E8))			// Palette control register
#define R_PPU_IRQ_EN			(*((volatile INT32U *) 0xD0500188))			// PPU IRQ enable register
#define R_PPU_IRQ_STATUS		(*((volatile INT32U *) 0xD050018C))			// PPU IRQ status register
#define R_PPU_SPRITE_DMA_SOURCE (*((volatile INT32U *) 0xD05001C0))			// PPU DMA source address register
#define R_PPU_SPRITE_DMA_TARGET (*((volatile INT32U *) 0xD05001C4))			// PPU DMA target address register
#define R_PPU_SPRITE_DMA_NUMBER (*((volatile INT32U *) 0xD05001C8))			// PPU DMA transfer number register
#define R_TV_FBI_ADDR			(*((volatile INT32U *) 0xD05001E0))			// Frame buffer address for TV
#define R_TFT_FBI_ADDR			(*((volatile INT32U *) 0xD050033C))			// Frame buffer address for TFT-LCD
#define R_PPU_MISC				(*((volatile INT32U *) 0xD05001F8))			// PPU MISC Control
#define R_PPU_ENABLE			(*((volatile INT32U *) 0xD05001FC))			// PPU enable register
#define R_FREE_SIZE				(*((volatile INT32U *) 0xD050036C))			// PPU Free Size Mode register
#define R_PPU_UI_CTRL			(*((volatile INT32U *) 0xD05003A0))			// UI control register
#define R_PPU_UI_ADDR			(*((volatile INT32U *) 0xD05003AC))			// UI Address
#define P_PPU_PALETTE_RAM0		((volatile INT32U *) 0xD0501000)			// Palette RAM0 base

/******************************************************************************
 * TV CONTROL REGISTERS
 ******************************************************************************/
#define R_TV_CTRL		(*((volatile INT32U *) 0xD05000F0))					// TV Control Register
#define R_TV_CTRL2		(*((volatile INT32U *) 0xD05000F4))					// TV Control2 Register
#define R_TV_SATURATION (*((volatile INT32U *) 0xD0500200))					// TV Saturation Control Register
#define R_TV_HUE		(*((volatile INT32U *) 0xD0500204))					// TV Hue Control Register
#define R_TV_BRIGHTNESS (*((volatile INT32U *) 0xD0500208))					// TV Brightness Control Register
#define R_TV_SHARPNESS	(*((volatile INT32U *) 0xD050020C))					// TV Sharpness Control Register
#define R_TV_Y_GAIN		(*((volatile INT32U *) 0xD0500210))					// TV Y Gain Control Register
#define R_TV_Y_DELAY	(*((volatile INT32U *) 0xD0500214))					// TV Y Delay Control Register
#define R_TV_V_POSITION (*((volatile INT32U *) 0xD0500218))					// TV Vertical Position Control Register
#define R_TV_H_POSITION (*((volatile INT32U *) 0xD050021C))					// TV Horizontal Position Control Register
#define R_TV_VIDEODAC	(*((volatile INT32U *) 0xD0500220))					// TV Video DAC Control Register
#define R_CSI_TG_CTRL1	(*((volatile INT32U *) 0xD0500244))
/******************************************************************************
 * TFT CONTROL REGISTERS
 ******************************************************************************/
#define R_TFT_CTRL				(*((volatile INT32U *) 0xD0500140))			// TFT Control Register
#define R_TFT_V_PERIOD			(*((volatile INT32U *) 0xD0500144))			// TFT Vertical Period Control Register
#define R_TFT_VS_WIDTH			(*((volatile INT32U *) 0xD0500148))			// TFT VSYNC Width Control Register
#define R_TFT_V_START			(*((volatile INT32U *) 0xD050014C))			// TFT Vertical Start Position Control Register
#define R_TFT_V_END				(*((volatile INT32U *) 0xD0500150))			// TFT Vertical End Position Control Register
#define R_TFT_H_PERIOD			(*((volatile INT32U *) 0xD0500154))			// TFT Horizontal Period Control Register
#define R_TFT_HS_WIDTH			(*((volatile INT32U *) 0xD0500158))			// TFT HSYNC Width Control Register
#define R_TFT_H_START			(*((volatile INT32U *) 0xD050015C))			// TFT Horizontal Start Position Control Register
#define R_TFT_H_END				(*((volatile INT32U *) 0xD0500160))			// TFT Horizontal End Position Control Register
#define R_TFT_LINE_RGB_ORDER	(*((volatile INT32U *) 0xD0500164))			// TFT Line RGB Order Control Register
#define R_TFT_STATUS			(*((volatile INT32U *) 0xD0500168))			// TFT Status Register
#define R_TFT_MEM_BUFF_WR		(*((volatile INT32U *) 0xD050016C))
#define R_TFT_MEM_BUFF_RD		(*((volatile INT32U *) 0xD0500170))
#define R_TFT_TE_CTRL			(*((volatile INT32U *) 0xD0500180))
#define R_TFT_TE_HS_WIDTH		(*((volatile INT32U *) 0xD0500184))
#define R_TFT_INT_EN			(*((volatile INT32U *) 0xD0500188))
#define R_TFT_INT_CLR			(*((volatile INT32U *) 0xD050018C))
#define R_TFT_VS_START			(*((volatile INT32U *) 0xD05001B0))
#define R_TFT_VS_END			(*((volatile INT32U *) 0xD05001B4))
#define R_TFT_HS_START			(*((volatile INT32U *) 0xD05001B8))
#define R_TFT_HS_END			(*((volatile INT32U *) 0xD05001BC))
#if 1
#define R_TFT2_CTRL				(*((volatile INT32U *) 0xD05002C0))	//bit[16]
#define R_TFT2_V_PERIOD			(*((volatile INT32U *) 0xD05002C4))
#define R_TFT2_VS_WIDTH			(*((volatile INT32U *) 0xD05002C8))
#define R_TFT2_V_START			(*((volatile INT32U *) 0xD05002CC))
#define R_TFT2_V_END			(*((volatile INT32U *) 0xD05002D0))
#define R_TFT2_H_PERIOD			(*((volatile INT32U *) 0xD05002D4))
#define R_TFT2_HS_WIDTH			(*((volatile INT32U *) 0xD05002D8))
#define R_TFT2_H_START			(*((volatile INT32U *) 0xD05002DC))
#define R_TFT2_H_END			(*((volatile INT32U *) 0xD05002E0))
#define R_TFT2_LINE_RGB_ORDER	(*((volatile INT32U *) 0xD05002E4))			// TFT Line RGB Order Control Register
#define R_TFT2_MEM_BUFF_WR		(*((volatile INT32U *) 0xD05002EC))
#define R_TFT2_MEM_BUFF_RD		(*((volatile INT32U *) 0xD05002F0))
#define R_TFT2_INTP_OUT_FACTOR	(*((volatile INT32U *) 0xD05002F4))
#define R_TFT2_INTP_OUT_OFFSET	(*((volatile INT32U *) 0xD05002F8))
#define R_TFT2_INTP_OUT_RESO	(*((volatile INT32U *) 0xD05002FC))
#define R_TFT2_MEM_BUFF_WR		(*((volatile INT32U *) 0xD05002EC))
#define R_TFT2_MEM_BUFF_RD		(*((volatile INT32U *) 0xD05002F0))

#else
#define R_TFT2_CTRL				(*((volatile INT32U *) 0xD05002C0))			// TFT Control Register
#define R_TFT2_V_PERIOD			(*((volatile INT32U *) 0xD05002C4))			// TFT Vertical Period Control Register
#define R_TFT2_VS_WIDTH			(*((volatile INT32U *) 0xD05002C8))			// TFT VSYNC Width Control Register
#define R_TFT2_V_START			(*((volatile INT32U *) 0xD05002CC))			// TFT Vertical Start Position Control Register
#define R_TFT2_V_END			(*((volatile INT32U *) 0xD05002D0))			// TFT Vertical End Position Control Register
#define R_TFT2_H_PERIOD			(*((volatile INT32U *) 0xD05002D4))			// TFT Horizontal Period Control Register
#define R_TFT2_HS_WIDTH			(*((volatile INT32U *) 0xD05002D8))			// TFT HSYNC Width Control Register
#define R_TFT2_H_START			(*((volatile INT32U *) 0xD05002DC))			// TFT Horizontal Start Position Control Register
#define R_TFT2_H_END			(*((volatile INT32U *) 0xD05002E0))			// TFT Horizontal End Position Control Register
#define R_TFT2_LINE_RGB_ORDER	(*((volatile INT32U *) 0xD05002E4))			// TFT Line RGB Order Control Register
#define R_TFT2_STATUS			(*((volatile INT32U *) 0xD05002E8))			// TFT Status Register
#define R_TFT2_VS_START			(*((volatile INT32U *) 0xD05002F4))
#define R_TFT2_VS_END			(*((volatile INT32U *) 0xD05002F8))
#define R_TFT2_HS_START			(*((volatile INT32U *) 0xD05002FC))
#define R_TFT2_HS_END			(*((volatile INT32U *) 0xD0500300))
#define R_TFT2_INTP_OUT_FACTOR	R_TFT2_VS_START
#define R_TFT2_INTP_OUT_RESO	R_TFT2_VS_END
#endif
#define R_TFT_TS_CKV			(*((volatile INT32U *) 0xD05003C0))
#define R_TFT_TW_CKV			(*((volatile INT32U *) 0xD05003C4))
#define R_TFT_TS_MISC			(*((volatile INT32U *) 0xD05003C8))
#define R_TFT_TS_POL			(*((volatile INT32U *) 0xD05003CC))
#define R_TFT_TS_STV			(*((volatile INT32U *) 0xD05003D0))
#define R_TFT_TW_STV			(*((volatile INT32U *) 0xD05003D4))
#define R_TFT_TS_STH			(*((volatile INT32U *) 0xD05003D8))
#define R_TFT_TW_STH			(*((volatile INT32U *) 0xD05003DC))
#define R_TFT_TS_OEV			(*((volatile INT32U *) 0xD05003E0))
#define R_TFT_TW_OEV			(*((volatile INT32U *) 0xD05003E4))
#define R_TFT_TS_LD				(*((volatile INT32U *) 0xD05003E8))
#define R_TFT_TW_LD				(*((volatile INT32U *) 0xD05003EC))
#define R_TFT_TAB0				(*((volatile INT32U *) 0xD05003F0))
#define R_TFT_TAB1				(*((volatile INT32U *) 0xD05003F4))
#define R_TFT_TAB2				(*((volatile INT32U *) 0xD05003F8))
#define R_TFT_TAB3				(*((volatile INT32U *) 0xD05003FC))
#define R_TFT_CLIP_V_START		(*((volatile INT32U *) 0xD05003B0))
#define R_TFT_CLIP_V_END		(*((volatile INT32U *) 0xD05003B4))
#define R_TFT_CLIP_H_START		(*((volatile INT32U *) 0xD05003B8))
#define R_TFT_CLIP_H_END		(*((volatile INT32U *) 0xD05003BC))
#define P_TFT_COLOR_MAP_BASE	((volatile INT32U *) 0xD0507000)			// Color mapping RAM base

/******************************************************************************
 * MIPI DSI CONTROL REGISTERS
 ******************************************************************************/
#define DSI_BASE				((volatile INT32U *) 0xD1500000)
#define R_DSI_VM_HT_CTRL		(*((volatile INT32U *) 0xD1500000))			//Horizontal Timing Control
#define R_DSI_VM_VT0_CTRL		(*((volatile INT32U *) 0xD1500004))			//Vertical 0 Timing Control
#define R_DSI_VM_VT1_CTRL		(*((volatile INT32U *) 0xD1500008))			//Vertical 1 Timing Control
#define R_DSI_VM_BLLP_CTRL		(*((volatile INT32U *) 0xD150000C))			//BLLP Timing
#define R_DSI_LPCK_CTRL			(*((volatile INT32U *) 0xD1500010))			//Low Power clock divider
#define R_DSI_LANE_TIMING_CTRL	(*((volatile INT32U *) 0xD1500014))			//Timing Control for CLK/Data Lane
#define R_DSI_CL_TM0_CTRL		(*((volatile INT32U *) 0xD1500018))			//Clock Lane Timing Control
#define R_DSI_CL_TM1_CTRL		(*((volatile INT32U *) 0xD150001C))			//Clock Lane Timing Control
#define R_DSI_DL_TM_CTRL		(*((volatile INT32U *) 0xD1500020))			//Data Lane Timing Control
#define R_DSI_VM_INPUT_CTRL		(*((volatile INT32U *) 0xD1500030))			//Video Mode Input format
#define R_DSI_BLK_CTRL			(*((volatile INT32U *) 0xD1500034))			//Operation Mode Control for Blanking Period
#define R_DSI_SPKT_HD_CTRL		(*((volatile INT32U *) 0xD1500024))			//Short Packet Header
#define R_DSI_LPKT_HD_CTRL		(*((volatile INT32U *) 0xD1500028))			//Long Packet Header
#define R_DSI_LPKT_PLD_CTRL		(*((volatile INT32U *) 0xD150002C))			//Long Packet Payload Control
#define R_DSI_OP_CTRL			(*((volatile INT32U *) 0xD1500038))			//Operation control
#define R_DSI_CTRL				(*((volatile INT32U *) 0xD150003C))
#define R_DSI_FIFO_STATUS		(*((volatile INT32U *) 0xD1500040))
#define R_DSI_BTA_CTRL			(*((volatile INT32U *) 0xD1500044))
#define R_DSI_LANE_SWAP			(*((volatile INT32U *) 0xD1500048))
#define R_DSI_RGBWC_CTRL		(*((volatile INT32U *) 0xD150004C))
#define R_DSI_RTN_RD_PORT		(*((volatile INT32U *) 0xD1500050))			//Return Data Entry Port
#define R_DSI_ACKERR_RSP		(*((volatile INT32U *) 0xD1500054))			//Ack Response Status Register
#define R_DSI_RSP_DBC			(*((volatile INT32U *) 0xD1500058))			//Response Data Byte Count
#define R_DSI_INT_STATUS		(*((volatile INT32U *) 0xD1500060))			//Interrupt Status
#define R_DSI_INT_EN_CTRL		(*((volatile INT32U *) 0xD1500064))			//Interrupt Enable
#define R_DSI_ERR_STATUS		(*((volatile INT32U *) 0xD1500068))			//Error Interrupt Status
#define R_DSI_STATUS			(*((volatile INT32U *) 0xD1500070))
#define R_DSI_WUD_CTRL			(*((volatile INT32U *) 0xD1500074))			//Wakeup Delay
#define R_DSI_CK_CTRL			(*((volatile INT32U *) 0xD1500078))
#define R_DSI_PHY_CTRL			(*((volatile INT32U *) 0xD1500090))


/******************************************************************************
 * DISP CONTROL REGISTERS
 ******************************************************************************/
#define DISP_BASE			0xD1600000

#define R_DISP_CTRL			(*((volatile INT32U *) 0xD1600000))				//Horizontal Timing Control
#define R_DISP_EDGE_CTRL0	(*((volatile INT32U *) 0xD1600004))				//Vertical 0 Timing Control
#define R_DISP_EDGE_CTRL1	(*((volatile INT32U *) 0xD1600008))				//Vertical 1 Timing Control
#define R_DISP_DLY_CTRL		(*((volatile INT32U *) 0xD160000C))				//BLLP Timing
#define R_DISP_UPDATE		(*((volatile INT32U *) 0xD160003C))				//BLLP Timing

#define R_DISP_R_GAMMA		(*((volatile INT32U *) 0xD1600400))				//BLLP Timing
#define R_DISP_G_GAMMA		(*((volatile INT32U *) 0xD1600800))				//BLLP Timing
#define R_DISP_B_GAMMA		(*((volatile INT32U *) 0xD1600C00))				//BLLP Timing


#define P_CC_MATX_PARA0		(((volatile INT32U *) (DISP_BASE + 0x0040)))
#define P_CC_MATX_PARA1		(((volatile INT32U *) (DISP_BASE + 0x0044)))
#define P_CC_MATX_PARA2		(((volatile INT32U *) (DISP_BASE + 0x0048)))
#define P_CC_MATX_PARA3		(((volatile INT32U *) (DISP_BASE + 0x004C)))
#define P_CC_MATX_PARA4		(((volatile INT32U *) (DISP_BASE + 0x0050)))
#define P_CC_MATX_PARA5		(((volatile INT32U *) (DISP_BASE + 0x0054)))

/********************************************************************************
*DISP CONTROL HUE BASE:Hue th1~12
*********************************************************************************/
//hue th1
#define P_TH1_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0058)))
#define P_TH1_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x005C)))
#define P_TH1_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0060)))
#define P_TH1_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x0064)))
#define P_TH1_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0068)))
#define P_TH1_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x006C)))
//hue th2
#define P_TH2_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0070)))
#define P_TH2_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x0074)))
#define P_TH2_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0078)))
#define P_TH2_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x007C)))
#define P_TH2_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0080)))
#define P_TH2_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x0084)))
//hue th3
#define P_TH3_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0088)))
#define P_TH3_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x008C)))
#define P_TH3_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0090)))
#define P_TH3_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x0094)))
#define P_TH3_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0098)))
#define P_TH3_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x009C)))
//hue th4
#define P_TH4_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x00A0)))
#define P_TH4_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x00A4)))
#define P_TH4_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x00A8)))
#define P_TH4_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x00AC)))
#define P_TH4_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x00B0)))
#define P_TH4_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x00B4)))
//hue th5
#define P_TH5_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x00B8)))
#define P_TH5_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x00BC)))
#define P_TH5_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x00C0)))
#define P_TH5_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x00C4)))
#define P_TH5_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x00C8)))
#define P_TH5_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x00CC)))
//hue th6
#define P_TH6_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x00D0)))
#define P_TH6_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x00D4)))
#define P_TH6_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x00D8)))
#define P_TH6_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x00DC)))
#define P_TH6_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x00E0)))
#define P_TH6_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x00E4)))
//hue th7
#define P_TH7_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x00E8)))
#define P_TH7_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x00EC)))
#define P_TH7_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x00F0)))
#define P_TH7_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x00F4)))
#define P_TH7_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x00F8)))
#define P_TH7_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x00FC)))
//hue th8
#define P_TH8_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0100)))
#define P_TH8_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x0104)))
#define P_TH8_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0108)))
#define P_TH8_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x010C)))
#define P_TH8_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0110)))
#define P_TH8_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x0114)))
//hue th9
#define P_TH9_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0118)))
#define P_TH9_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x011C)))
#define P_TH9_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0120)))
#define P_TH9_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x0124)))
#define P_TH9_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0128)))
#define P_TH9_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x012C)))
//hue th10
#define P_TH10_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0130)))
#define P_TH10_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x0134)))
#define P_TH10_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0138)))
#define P_TH10_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x013C)))
#define P_TH10_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0140)))
#define P_TH10_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x0144)))
//hue th11
#define P_TH11_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0148)))
#define P_TH11_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x014C)))
#define P_TH11_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0150)))
#define P_TH11_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x0154)))
#define P_TH11_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0158)))
#define P_TH11_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x015C)))
//hue th12
#define P_TH12_HUE_MATX_PARA0	(((volatile INT32U *) (DISP_BASE + 0x0160)))
#define P_TH12_HUE_MATX_PARA1	(((volatile INT32U *) (DISP_BASE + 0x0164)))
#define P_TH12_HUE_MATX_PARA2	(((volatile INT32U *) (DISP_BASE + 0x0168)))
#define P_TH12_HUE_MATX_PARA3	(((volatile INT32U *) (DISP_BASE + 0x016C)))
#define P_TH12_HUE_MATX_PARA4	(((volatile INT32U *) (DISP_BASE + 0x0170)))
#define P_TH12_HUE_MATX_PARA5	(((volatile INT32U *) (DISP_BASE + 0x0174)))

#define P_HUE_MATX_THR_1_3		(((volatile INT32U *) (DISP_BASE + 0x0180)))
#define P_HUE_MATX_THR_4_6		(((volatile INT32U *) (DISP_BASE + 0x0184)))
#define P_HUE_MATX_THR_7_9		(((volatile INT32U *) (DISP_BASE + 0x0188)))
#define P_HUE_MATX_THR_10_12	(((volatile INT32U *) (DISP_BASE + 0x018C)))
#define P_HUE_MATX_LIMIT		(((volatile INT32U *) (DISP_BASE + 0x0190)))

#define P_DISP_R_GAMMA		(((volatile INT32U *) (DISP_BASE + 0x0400)))				//BLLP Timing
#define P_DISP_G_GAMMA		(((volatile INT32U *) (DISP_BASE + 0x0800)))				//BLLP Timing
#define P_DISP_B_GAMMA		(((volatile INT32U *) (DISP_BASE + 0x0C00)))				//BLLP Timing


//HUE BASE
#define P_TH1_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x0058)))
#define P_TH2_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x0070)))
#define P_TH3_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x0088)))
#define P_TH4_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x00A0)))
#define P_TH5_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x00B8)))
#define P_TH6_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x00D0)))
#define P_TH7_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x00E8)))
#define P_TH8_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x0100)))
#define P_TH9_HUE_MATX_BASE		(((volatile INT32U *) (DISP_BASE + 0x0118)))
#define P_TH10_HUE_MATX_BASE	(((volatile INT32U *) (DISP_BASE + 0x0130)))
#define P_TH11_HUE_MATX_BASE	(((volatile INT32U *) (DISP_BASE + 0x0148)))
#define P_TH12_HUE_MATX_BASE	(((volatile INT32U *) (DISP_BASE + 0x0160)))


/*****************************************************************************
* STN CONTROL REGISTERS
******************************************************************************/
#define R_STN_CTRL0		(*((volatile INT32U *) 0xD050017C))					// STN Control Register 0
#define R_STN_SEG		(*((volatile INT32U *) 0xD0500200))					// STN Segment Register
#define R_STN_COM		(*((volatile INT32U *) 0xD0500204))					// STN Column Register
#define R_STN_PIC_COM	(*((volatile INT32U *) 0xD0500208))					// STN Picture Column Register
#define R_STN_CPWAIT	(*((volatile INT32U *) 0xD050020C))					// STN CP Wait Register
#define R_STN_CTRL1		(*((volatile INT32U *) 0xD0500210))					// STN Control Register 1
#define R_STN_GTG_SEG	(*((volatile INT32U *) 0xD0500214))					// STN Global Timing Generator Segment Register
#define R_STN_GTG_COM	(*((volatile INT32U *) 0xD0500218))					// STN Global Timing Generator Column Register
#define R_STN_SEG_CLIP	(*((volatile INT32U *) 0xD050021C))					// STN Clipping Start Segment Register
#define R_STN_COM_CLIP	(*((volatile INT32U *) 0xD0500144))					// STN Clipping Start Column Register

/******************************************************************************
 * CMOS SENSOR INTERFACE (CSI): CSI0:
 ******************************************************************************/
#define P_CSI0_CONTROL_BASE	((volatile INT32U *) 0xD0500238)
#define P_CSI1_CONTROL_BASE	((volatile INT32U *) 0xD0500400)

#define P_CSI_MD_FBADDR		((volatile INT32U *) 0xD0500254)    // CSI Motion Detect Buffer Start Address Register
#define P_CSI_MD_FBADDRH	((volatile INT32U *) 0xD0500298)
#define P_CSI_TG_FBSADDR	((volatile INT32U *) 0xD0500278)    // CSI Frame Buffer Start Address Register

#define R_CSI_TG_CTRL0		(*((volatile INT32U *) 0xD0500240)) // CSI Timing Generator Control Register 1
#define R_CSI_TG_CTRL1		(*((volatile INT32U *) 0xD0500244)) // CSI Timing Generator Control Register 2
#define R_CSI_TG_HLSTART	(*((volatile INT32U *) 0xD0500248)) // CSI Horizontal Latch Start Register
#define R_CSI_TG_HEND		(*((volatile INT32U *) 0xD050024C)) // CSI Horizontal End Register
#define R_CSI_TG_VL0START	(*((volatile INT32U *) 0xD0500250)) // CSI Field 0 Vertical Start Register
#define R_CSI_MD_FBADDR		(*((volatile INT32U *) 0xD0500254)) // CSI Motion Detect Buffer Start Address Register
#define R_CSI_TG_VEND		(*((volatile INT32U *) 0xD0500258)) // CSI Vertical End Register
#define R_CSI_TG_HSTART		(*((volatile INT32U *) 0xD050025C)) // CSI Horizontal Start Register
#define R_CSI_MD_RGBL		(*((volatile INT32U *) 0xD0500260)) // CSI Motion Detect RGB/YUV Lo-Word Register
#define R_CSI_SEN_CTRL		(*((volatile INT32U *) 0xD0500264)) // CSI Attribute Control Register
#define R_CSI_TG_BSUPPER	(*((volatile INT32U *) 0xD0500268)) // CSI Blue Screen Upper Limit Control Register
#define R_CSI_TG_BSLOWER	(*((volatile INT32U *) 0xD050026C)) // CSI Blue Screen Lower Limit Control Register
#define R_CSI_MD_RGBH		(*((volatile INT32U *) 0xD0500270)) // CSI Motion Detect RGB/YUV Hi-Word Register
#define R_CSI_MD_CTRL		(*((volatile INT32U *) 0xD0500274)) // CSI Motion Detect Control Register
#define R_CSI_TG_FBSADDR	(*((volatile INT32U *) 0xD0500278)) // CSI Frame Buffer Start Address Register
#define R_CSI_TG_VL1START	(*((volatile INT32U *) 0xD0500280)) // CSI Field 1 Vertical Start Register
#define R_CSI_TG_HWIDTH		(*((volatile INT32U *) 0xD0500284)) // CSI Horizontal Width Control Register
#define R_CSI_TG_VHEIGHT	(*((volatile INT32U *) 0xD0500288)) // CSI Vertical Width Control Register
#define R_CSI_TG_CUTSTART	(*((volatile INT32U *) 0xD050028C)) // CSI Cut Region Start Address Register
#define R_CSI_TG_CUTSIZE	(*((volatile INT32U *) 0xD0500290)) // CSI Cut Size Register
#define R_CSI_TG_VSTART		(*((volatile INT32U *) 0xD0500294)) // CSI Vertical Start Register
#define R_CSI_TG_HRATIO		(*((volatile INT32U *) 0xD050029C)) // CSI Horizontal Compress Ratio Control Register
#define R_CSI_TG_VRATIO		(*((volatile INT32U *) 0xD05002A0)) // CSI Vertical Compress Ratio Control Register
#define R_CSI_MD_HPOS		(*((volatile INT32U *) 0xD05002A4)) // CSI Motion Detect Horizontal Hit Position Register
#define R_CSI_MD_VPOS		(*((volatile INT32U *) 0xD05002A8)) // CSI Motion Detect Vertical Hit Position Register
#define R_TGR_IRQ_EN		(*((volatile INT32U *) 0xD050023C))
#define R_TGR_IRQ_STATUS	(*((volatile INT32U *) 0xD0500238))
#define P_CSI_TG_FBSADDR_B	((volatile INT32U *) 0xD05002AC)


/******************************************************************************
 * RAMDOM CONTROL REGISTERS
 ******************************************************************************/
#define R_RANDOM0			(*((volatile INT32U *) 0xD0500380))
#define R_RANDOM1			(*((volatile INT32U *) 0xD0500384))

/******************************************************************************
 * DEFLICKER INTERFACE CONTROL REGISTERS
 ******************************************************************************/
#define R_DEFLICKER_CTRL	(*((volatile INT32U *) 0xD0800000))				// De-flicker control register
#define R_DEFLICKER_INPTRL	(*((volatile INT32U *) 0xD0800004))				// De-flicker input address register
#define R_DEFLICKER_OUTPTRL	(*((volatile INT32U *) 0xD0800008))				// De-flicker output address register
#define R_DEFLICKER_PARA	(*((volatile INT32U *) 0xD080000C))				// De-flicker parameter register
#define R_DEFLICKER_INT		(*((volatile INT32U *) 0xD080007C))				// De-flicker interrupt status register

/******************************************************************************
 * GTE CONTROL REGISTERS
 ******************************************************************************/
#define R_GTE0_ACT_M4X4		(*((volatile INT32U *) 0xF6800000))
#define R_GTE0_ACT_M3X3		(*((volatile INT32U *) 0xF6800004))
#define R_GTE0_ACT_INNER	(*((volatile INT32U *) 0xF6800008))
#define R_GTE0_ACT_OUTER	(*((volatile INT32U *) 0xF680000C))
#define R_GTE1_ACT_M4X4		(*((volatile INT32U *) 0xF6800010))
#define R_GTE1_ACT_M3X3		(*((volatile INT32U *) 0xF6800014))
#define R_GTE1_ACT_INNER	(*((volatile INT32U *) 0xF6800018))
#define R_GTE1_ACT_OUTER	(*((volatile INT32U *) 0xF680001C))
#define R_GTE_A0			(*((volatile INT32U *) 0xF6004000))
#define R_GTE_A1			(*((volatile INT32U *) 0xF6004004))
#define R_GTE_A2			(*((volatile INT32U *) 0xF6004008))
#define R_GTE_A3			(*((volatile INT32U *) 0xF600400C))
#define R_GTE_A4			(*((volatile INT32U *) 0xF6004010))
#define R_GTE_A5			(*((volatile INT32U *) 0xF6004014))
#define R_GTE_A6			(*((volatile INT32U *) 0xF6004018))
#define R_GTE_A7			(*((volatile INT32U *) 0xF600401C))
#define R_GTE_A8			(*((volatile INT32U *) 0xF6004020))
#define R_GTE_A9			(*((volatile INT32U *) 0xF6004024))
#define R_GTE_AA			(*((volatile INT32U *) 0xF6004028))
#define R_GTE_AB			(*((volatile INT32U *) 0xF600402C))
#define R_GTE_AC			(*((volatile INT32U *) 0xF6004030))
#define R_GTE_AD			(*((volatile INT32U *) 0xF6004034))
#define R_GTE_AE			(*((volatile INT32U *) 0xF6004038))
#define R_GTE_AF			(*((volatile INT32U *) 0xF600403C))
#define R_GTE0_XI			(*((volatile INT32U *) 0xF6004040))
#define R_GTE0_YI			(*((volatile INT32U *) 0xF6004044))
#define R_GTE0_ZI			(*((volatile INT32U *) 0xF6004048))
#define R_GTE0_WI			(*((volatile INT32U *) 0xF600404C))
#define R_GTE1_XI			(*((volatile INT32U *) 0xF6004050))
#define R_GTE1_YI			(*((volatile INT32U *) 0xF6004054))
#define R_GTE1_ZI			(*((volatile INT32U *) 0xF6004058))
#define R_GTE1_WI			(*((volatile INT32U *) 0xF600405C))
#define R_GTE0_XO			(*((volatile INT32U *) 0xF6004060))
#define R_GTE0_YO			(*((volatile INT32U *) 0xF6004064))
#define R_GTE0_ZO			(*((volatile INT32U *) 0xF6004068))
#define R_GTE0_WO			(*((volatile INT32U *) 0xF600406C))
#define R_GTE1_XO			(*((volatile INT32U *) 0xF6004070))
#define R_GTE1_YO			(*((volatile INT32U *) 0xF6004074))
#define R_GTE1_ZO			(*((volatile INT32U *) 0xF6004078))
#define R_GTE1_WO			(*((volatile INT32U *) 0xF600407C))
#define R_GTE_MODE			(*((volatile INT32U *) 0xF6004080))
#define R_GTE_FORMAT		(*((volatile INT32U *) 0xF6004084))
#define R_GTE0_OF			(*((volatile INT32U *) 0xF600408C))
#define R_GTE1_OF			(*((volatile INT32U *) 0xF600409C))
#define R_GTE_DIVA			(*((volatile INT32U *) 0xF60040A0))
#define R_GTE_DIVB			(*((volatile INT32U *) 0xF60040A4))
#define R_GTE_DIVOF			(*((volatile INT32U *) 0xF60040A8))
#define R_GTE_DIVO			(*((volatile INT32U *) 0xF60040AC))
#define R_GTE_DIVR			(*((volatile INT32U *) 0xF60040B0))

/******************************************************************************
 * Session: Scaler SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Scaler SFR
 ******************************************************************************/
/******************************************************************************
 * Scaler0: 0xD0600000    Scaler1: 0xD1000000
 ******************************************************************************/
#define SCALER0_BASE	0xD0600000
#define SCALER1_BASE	0xD1000000

/******************************************************************************
 * PIPLINE SCALER
 ******************************************************************************/
#define PIPELINE_SCALERA_BASE	((volatile INT32U *) 0xD1300000)
#define PIPELINE_SCALERB_BASE	((volatile INT32U *) 0xD1400000)

/******************************************************************************
 * Session: JPEG SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: JPEG SFR
 ******************************************************************************/
/******************************************************************************
 * JPEG0: 0xD0700000 JPEG1: 0xD0400000
 ******************************************************************************/
#define P_JPG0_CONTROL_BASE				((volatile INT32U *) 0xD0701204)
#define P_JPG1_CONTROL_BASE				((volatile INT32U *) 0xD0401204)
#define P_JPG0_HUFFMAN_TABLE_BASE		((volatile INT32U *) 0xD0703000)
#define P_JPG1_HUFFMAN_TABLE_BASE		((volatile INT32U *) 0xD0403000)
#define P_JPG0_AC_HUFFVAL_TABLE_BASE	((volatile INT32U *) 0xD0704000)
#define P_JPG1_AC_HUFFVAL_TABLE_BASE	((volatile INT32U *) 0xD0404000)
#define P_JPG0_QUANTIZATION_TABLE_BASE	((volatile INT32U *) 0xD0700000)
#define P_JPG1_QUANTIZATION_TABLE_BASE	((volatile INT32U *) 0xD0400000)

//JPEG0
#define R_JPG_Y_FRAME_ADDR				(*((volatile INT32U *) 0xD0702380))
#define R_JPG_U_FRAME_ADDR				(*((volatile INT32U *) 0xD0702384))
#define R_JPG_V_FRAME_ADDR				(*((volatile INT32U *) 0xD0702388))

//JPEG1
#define R_JPG1_Y_FRAME_ADDR				(*((volatile INT32U *) 0xD0402380))
#define R_JPG1_U_FRAME_ADDR				(*((volatile INT32U *) 0xD0402384))
#define R_JPG1_V_FRAME_ADDR				(*((volatile INT32U *) 0xD0402388))
/******************************************************************************
 * Session: Cache controller SFR
 * Layer: Driver Layer 1
 * Date: 2008/01/25
 * Note: Cache controller SFR
 ******************************************************************************/
/******************************************************************************
 * Cache controller: 0xFF000000
 ******************************************************************************/
#define CACHE_BASE				0xFF000000

#define P_CACHE_VALID_LOCK_TAG	((volatile INT32U *) 0xF7000000)

//#define P_CACHE_VALID_LOCK_TAG		((volatile INT32U *) (CACHE_BASE - 0x8000000))
#define R_CACHE_CTRL				(*((volatile INT32U *) (CACHE_BASE + 0x00)))
#define R_CACHE_CFG					(*((volatile INT32U *) (CACHE_BASE + 0x04)))
#define R_CACHE_INVALID_LINE		(*((volatile INT32U *) (CACHE_BASE + 0x08)))
#define R_CACHE_LOCKDOWN			(*((volatile INT32U *) (CACHE_BASE + 0x0C)))
#define R_CACHE_DRAIN_WRITE_BUFFER	(*((volatile INT32U *) (CACHE_BASE + 0x10)))
#define R_CACHE_DRAIN_LINE			(*((volatile INT32U *) (CACHE_BASE + 0x14)))
#define R_CACHE_INVALID_BANK		(*((volatile INT32U *) (CACHE_BASE + 0x18)))
#define R_CACHE_INVALID_RANGE_SEZE	(*((volatile INT32U *) (CACHE_BASE + 0x1C)))
#define R_CACHE_INVALID_RANGE_ADDR	(*((volatile INT32U *) (CACHE_BASE + 0x20)))
#define R_CACHE_ACCESS_COUNT		(*((volatile INT32U *) (CACHE_BASE + 0x40)))
#define R_CACHE_HIT_COUNT			(*((volatile INT32U *) (CACHE_BASE + 0x44)))

/******************************************************************************
 * I2C control 0xC00B0000
 ******************************************************************************/
#define I2C0_BASE		0xC00B0000
#define I2C1_BASE		0xC00C0000

#define R_I2C0_ICCR		(*((volatile INT32U *) 0xC00B0000))
#define R_I2C0_ICSR		(*((volatile INT32U *) 0xC00B0004))
#define R_I2C0_TXCLKLSB (*((volatile INT32U *) 0xC00B0014))
#define R_I2C0_MISC		(*((volatile INT32U *) 0xC00B0018))
#define R_I2C0_SLAVID	(*((volatile INT32U *) 0xC00B0020))
#define R_I2C0_DELY		(*((volatile INT32U *) 0xC00B0028))
#define R_I2C1_ICCR		(*((volatile INT32U *) 0xC00C0000))
#define R_I2C1_ICSR		(*((volatile INT32U *) 0xC00C0004))
#define R_I2C1_TXCLKLSB	(*((volatile INT32U *) 0xC00C0014))
#define R_I2C1_MISC		(*((volatile INT32U *) 0xC00C0018))
#define R_I2C1_SLAVID	(*((volatile INT32U *) 0xC00C0020))
#define R_I2C0_DELY		(*((volatile INT32U *) 0xC00B0028))

/******************************************************************************
 * Analog TFT CONTROL REGISTERS
 ******************************************************************************/
#define R_ANALOG_TFT_CTRL_L		(*((volatile INT32U *) 0xC0130080))
#define R_ANALOG_TFT_CTRL_H		(*((volatile INT32U *) 0xC0130084))
#define R_ANALOG_TFT_CTRL2_L	(*((volatile INT32U *) 0xC0130088))
#define R_ANALOG_TFT_CTRL2_H	(*((volatile INT32U *) 0xC013008C))
#define R_ANALOG_TFT_TS_STH_L	(*((volatile INT32U *) 0xC0130090))
#define R_ANALOG_TFT_TS_STH_H	(*((volatile INT32U *) 0xC0130094))
#define R_ANALOG_TFT_H_START_L	(*((volatile INT32U *) 0xC0130098))
#define R_ANALOG_TFT_H_START_H	(*((volatile INT32U *) 0xC013009C))
#define R_ANALOG_TFT_V_START	(*((volatile INT32U *) 0xC01300A0))
#define R_ANALOG_TFT_TW_STH		(*((volatile INT32U *) 0xC01300A4))
#define R_ANALOG_TFT_T_HS2OEH	(*((volatile INT32U *) 0xC01300A8))
#define R_ANALOG_TFT_TW_OEH		(*((volatile INT32U *) 0xC01300AC))
#define R_ANALOG_TFT_T_HS2CKV	(*((volatile INT32U *) 0xC01300B0))
#define R_ANALOG_TFT_TW_CKV		(*((volatile INT32U *) 0xC01300B4))
#define R_ANALOG_TFT_T_HS2OEV	(*((volatile INT32U *) 0xC01300B8))
#define R_ANALOG_TFT_TW_OEV		(*((volatile INT32U *) 0xC01300BC))
#define R_ANALOG_TFT_TS_STV		(*((volatile INT32U *) 0xC01300C0))
#define R_ANALOG_TFT_CLK_DLY	(*((volatile INT32U *) 0xC01300C4))
#define R_ANALOG_TFT_AG			(*((volatile INT32U *) 0xC01300C8))
#define R_ANALOG_TFT_TS_POL		(*((volatile INT32U *) 0xC01300CC))
#define R_ANALOG_TFT_AG_H_START	(*((volatile INT32U *) 0xC0130100))
#define R_ANALOG_TFT_AG_V_START	(*((volatile INT32U *) 0xC0130104))

/******************************************************************************
 *IR RX for GPL326xx
 ******************************************************************************/
#define R_IR_RX_CTRL	(*((volatile INT32U *) 0xC0140000))
#define R_IR_RX_DATA	(*((volatile INT32U *) 0xC0140004))
#define R_IR_RX_PWR		(*((volatile INT32U *) 0xC0140008))

/******************************************************************************
 *MIC
 ******************************************************************************/
#define R_MIC_SETUP 	(*((volatile INT32U *) 0xC00D0040))
#define R_MIC_BOOST		(*((volatile INT32U *) 0xC00D0044))

/******************************************************************************
 *Digital AGC
 ******************************************************************************/
#define R_DAGC_CTRL		(*((volatile INT32U *) 0xC00D0070))
#define R_DAGC_TIME		(*((volatile INT32U *) 0xC00D0074))
#define R_DAGC_ENABLE	(*((volatile INT32U *) 0xC00D0078))
#define R_DAGC_STATUS	(*((volatile INT32U *) 0xC00D007C))
#define R_DAGC_UTHRES	(*((volatile INT32U *) 0xC00D0058))

/******************************************************************************
 * MIPI control: 0xD0F0000
 ******************************************************************************/
#define MIPI1_BASE	0xD1000000				//support 1-lane
#define MIPI0_BASE	0xD0F00000				//support 2-lane /1-lane

/******************************************************************************
 *I2S
 ******************************************************************************/
#define I2S0_BASE	0xC0200000
#define I2S1_BASE	0xC0210000
#define I2S2_BASE	0xC0220000
#define I2S3_BASE	0xC0230000

/******************************************************************************
 * I2S_TX: 0xC0200000
 ******************************************************************************/
#define P_I2STX_DATA	(((volatile INT32U *) (I2S0_BASE + 0x0004)))
#define P_I2S1TX_DATA	(((volatile INT32U *) (I2S1_BASE + 0x0004)))
#define P_I2S2TX_DATA	(((volatile INT32U *) (I2S2_BASE + 0x0004)))
#define P_I2S3TX_DATA	(((volatile INT32U *) (I2S3_BASE + 0x0004)))
#define R_I2STX_CTRL	(*((volatile INT32U *) (I2S0_BASE + 0x0000)))
#define R_I2STX_DATA	(*((volatile INT32U *) (I2S0_BASE + 0x0004)))
#define R_I2STX_STATUS	(*((volatile INT32U *) (I2S0_BASE + 0x0008)))

/******************************************************************************
 * I2S_RX: 0xC0200010
 ******************************************************************************/
#define P_I2SRX_DATA	(((volatile INT32U *) (I2S0_BASE + 0x0014)))
#define P_I2S1RX_DATA	(((volatile INT32U *) (I2S1_BASE + 0x0014)))
#define P_I2S2RX_DATA	(((volatile INT32U *) (I2S2_BASE + 0x0014)))
#define P_I2S3RX_DATA	(((volatile INT32U *) (I2S3_BASE + 0x0014)))
#define R_I2SRX_CTRL	(*((volatile INT32U *) (I2S0_BASE + 0x0010)))
#define R_I2SRX_DATA	(*((volatile INT32U *) (I2S0_BASE + 0x0014)))
#define R_I2SRX_STATUS	(*((volatile INT32U *) (I2S0_BASE + 0x0018)))

/******************************************************************************
 * Sca2Tft: 0xC0160000   CsiMux: 0xC0170000	Csi2Sca: 0xC0180000
 ******************************************************************************/
#define P_SCA2TFT_BASE		((volatile INT32U *) 0xC0160000)
#define P_CSIMUX_BASE		((volatile INT32U *) 0xC0170000)
#define P_CSI2SCA_BASE		((volatile INT32U *) 0xC0180000)
#define R_PROTECT_STATUS	(*((volatile INT32U *) 0xC0130008))

/******************************************************************************
 * CONV422TO420: 0xC0190000
 ******************************************************************************/
#define R_CONV422_BUF_A_ADDR	(*((volatile INT32U *) 0xC0190008))
#define R_CONV422_BUF_B_ADDR	(*((volatile INT32U *) 0xC019000C))
#define R_CONV422_IMG_WIDTH		(*((volatile INT32U *) 0xC0190010))
#define R_CONV422_IMG_HEIGHT	(*((volatile INT32U *) 0xC0190014))
#define R_CONV422_CTRL			(*((volatile INT32U *) 0xC0190018))
#define R_CONV422_DEPTH			(*((volatile INT32U *) 0xC019001C))
#define R_CONV422_LINE			(*((volatile INT32U *) 0xC0190020))
#define R_CONV422_LINE_A		(*((volatile INT32U *) 0xC0190024))
#define R_CONV422_LINE_B		(*((volatile INT32U *) 0xC0190028))

/******************************************************************************
 * CONV420TO422: 0xC01B0000
 ******************************************************************************/
#define R_CONV420_CTRL				(*((volatile INT32U *) 0xC01B0000))
#define R_CONV420_LINE_CTRL			(*((volatile INT32U *) 0xC01B0004))
#define R_CONV420_IN_A_ADDR			(*((volatile INT32U *) 0xC01B0008))
#define R_CONV420_IN_B_ADDR			(*((volatile INT32U *) 0xC01B000C))
#define R_CONV420_MASTER_MASK_INT	(*((volatile INT32U *) 0xC01B0010))

/******************************************************************************
 * CDSP: 0xD0800000
 ******************************************************************************/
#define CDSP_BASE							0xD0800000
#define P_CDSP_MACRO_CTRL					(volatile INT32U *) (CDSP_BASE + 0x000)

// cdsp
#define R_CDSP_MACRO_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x000))
#define R_CDSP_BADPIX_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x004))
#define R_CDSP_BADPIX_CTHR					(*(volatile INT32U *) (CDSP_BASE + 0x008))
#define R_CDSP_YUVSP_EFFECT_OFFSET			(*(volatile INT32U *) (CDSP_BASE + 0x00C))
#define R_CDSP_IMG_TYPE						(*(volatile INT32U *) (CDSP_BASE + 0x010))
#define R_CDSP_YUVSP_EFFECT_SCALER			(*(volatile INT32U *) (CDSP_BASE + 0x014))
#define R_CDSP_OPB_CTRL						(*(volatile INT32U *) (CDSP_BASE + 0x018))
#define R_CDSP_YUVSP_EFFECT_BTHR			(*(volatile INT32U *) (CDSP_BASE + 0x01C))
#define R_CDSP_OPB_TYPE						(*(volatile INT32U *) (CDSP_BASE + 0x020))
#define R_CDSP_OPB_HOFFSET					(*(volatile INT32U *) (CDSP_BASE + 0x024))
#define R_CDSP_OPB_VOFFSET					(*(volatile INT32U *) (CDSP_BASE + 0x028))
#define R_CDSP_OPB_RAVG						(*(volatile INT32U *) (CDSP_BASE + 0x040))
#define R_CDSP_OPB_GRAVG					(*(volatile INT32U *) (CDSP_BASE + 0x044))
#define R_CDSP_OPB_BAVG						(*(volatile INT32U *) (CDSP_BASE + 0x048))
#define R_CDSP_OPB_GBAVG					(*(volatile INT32U *) (CDSP_BASE + 0x04C))
#define R_CDSP_DUMMY						(*(volatile INT32U *) (CDSP_BASE + 0x050))
#define R_CDSP_LENS_CMP_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x080))
#define R_CDSP_CDSP_VVALID					(*(volatile INT32U *) (CDSP_BASE + 0x084))
#define R_CDSP_LENS_CMP_XOFFSET_MAP			(*(volatile INT32U *) (CDSP_BASE + 0x088))
#define R_CDSP_LENS_CMP_YOFFSET_MAP			(*(volatile INT32U *) (CDSP_BASE + 0x08C))
#define R_CDSP_LENS_CMP_YINSTEP_MAP			(*(volatile INT32U *) (CDSP_BASE + 0x090))
#define R_CDSP_HSCALE_EVEN_PVAL				(*(volatile INT32U *) (CDSP_BASE + 0x094))
#define R_CDSP_IM_XCENT						(*(volatile INT32U *) (CDSP_BASE + 0x098))
#define R_CDSP_IM_YCENT						(*(volatile INT32U *) (CDSP_BASE + 0x09C))
#define R_CDSP_HRAW_SCLDW_FACTOR			(*(volatile INT32U *) (CDSP_BASE + 0x0A0))
#define R_CDSP_HSCALE_ODD_PVAL				(*(volatile INT32U *) (CDSP_BASE + 0x0A4))
#define R_CDSP_VYUV_SCLDW_FACTOR			(*(volatile INT32U *) (CDSP_BASE + 0x0A8))
#define R_CDSP_VSCALE_ACC_INIT				(*(volatile INT32U *) (CDSP_BASE + 0x0AC))
#define R_CDSP_HYUV_SCLDW_FACTOR			(*(volatile INT32U *) (CDSP_BASE + 0x0B0))
#define R_CDSP_HSCALE_ACC_INIT				(*(volatile INT32U *) (CDSP_BASE + 0x0B4))
#define R_CDSP_SCLDW_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x0B8))
#define R_CDSP_SCALE_FACTOR_CTRL			(*(volatile INT32U *) (CDSP_BASE + 0x0BC))
#define R_CDSP_WHBAL_RSETTING				(*(volatile INT32U *) (CDSP_BASE + 0x0C0))
#define R_CDSP_WHBAL_GRSETTING				(*(volatile INT32U *) (CDSP_BASE + 0x0C4))
#define R_CDSP_WHBAL_BSETTING				(*(volatile INT32U *) (CDSP_BASE + 0x0C8))
#define R_CDSP_WHBAL_GBSETTING				(*(volatile INT32U *) (CDSP_BASE + 0x0CC))
#define R_CDSP_YUVSPEC_MODE					(*(volatile INT32U *) (CDSP_BASE + 0x0D0))
#define R_CDSP_GLOBAL_GAIN					(*(volatile INT32U *) (CDSP_BASE + 0x0D4))
#define R_CDSP_IMCROP_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x0D8))
#define R_CDSP_IMCROP_HOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x0DC))
#define R_CDSP_IMCROP_HSIZE					(*(volatile INT32U *) (CDSP_BASE + 0x0E0))
#define R_CDSP_IMCROP_VOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x0E4))
#define R_CDSP_IMCROP_VSIZE					(*(volatile INT32U *) (CDSP_BASE + 0x0E8))
#define R_CDSP_INP_DENOISE_THR				(*(volatile INT32U *) (CDSP_BASE + 0x0EC))
#define R_CDSP_INP_MIRROR_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x0F0))
#define R_CDSP_RGB_SPEC_ROT_MODE			(*(volatile INT32U *) (CDSP_BASE + 0x0F4))
#define R_CDSP_HPF_LCOEF0					(*(volatile INT32U *) (CDSP_BASE + 0x100))
#define R_CDSP_HPF_LCOEF1					(*(volatile INT32U *) (CDSP_BASE + 0x104))
#define R_CDSP_HPF_LCOEF2					(*(volatile INT32U *) (CDSP_BASE + 0x108))
#define R_CDSP_LH_DIV_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x10C))
#define R_CDSP_INP_EDGE_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x110))
#define R_CDSP_INP_QTHR						(*(volatile INT32U *) (CDSP_BASE + 0x114))
#define R_CDSP_INP_QCNT						(*(volatile INT32U *) (CDSP_BASE + 0x118))
#define R_CDSP_CC_COF0						(*(volatile INT32U *) (CDSP_BASE + 0x11C))
#define R_CDSP_CC_COF1						(*(volatile INT32U *) (CDSP_BASE + 0x120))
#define R_CDSP_CC_COF2						(*(volatile INT32U *) (CDSP_BASE + 0x124))
#define R_CDSP_CC_COF3						(*(volatile INT32U *) (CDSP_BASE + 0x128))
#define R_CDSP_CC_COF4						(*(volatile INT32U *) (CDSP_BASE + 0x12C))
#define R_CDSP_RB_CLAMP_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x134))
#define R_CDSP_UVSCALE_COND0				(*(volatile INT32U *) (CDSP_BASE + 0x138))
#define R_CDSP_UVSCALE_COND1				(*(volatile INT32U *) (CDSP_BASE + 0x13C))
#define R_CDSP_YUV_CTRL						(*(volatile INT32U *) (CDSP_BASE + 0x140))
#define R_CDSP_BIST_EN						(*(volatile INT32U *) (CDSP_BASE + 0x144))
#define R_CDSP_DENOISE_SETTING				(*(volatile INT32U *) (CDSP_BASE + 0x148))
#define R_CDSP_HUE_ROT_U					(*(volatile INT32U *) (CDSP_BASE + 0x14C))
#define R_CDSP_HUE_ROT_V					(*(volatile INT32U *) (CDSP_BASE + 0x150))
#define R_CDSP_YUV_RANGE					(*(volatile INT32U *) (CDSP_BASE + 0x154))
#define R_CDSP_INTEN						(*(volatile INT32U *) (CDSP_BASE + 0x158))
#define R_CDSP_GATING_CLK_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x15C))
#define R_CDSP_YUV_CORING_SETTING			(*(volatile INT32U *) (CDSP_BASE + 0x160))
#define R_CDSP_INT							(*(volatile INT32U *) (CDSP_BASE + 0x164))
#define R_CDSP_BIST_FAIL					(*(volatile INT32U *) (CDSP_BASE + 0x168))
#define R_CDSP_PROBE_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x16C))
#define R_CDSP_EXT_BANK_SIZE				(*(volatile INT32U *) (CDSP_BASE + 0x170))
#define R_CDSP_YUV_AVG_LPF_TYPE				(*(volatile INT32U *) (CDSP_BASE + 0x174))
#define R_CDSP_EXT_LINE_SIZE				(*(volatile INT32U *) (CDSP_BASE + 0x178))
#define R_CDSP_RST							(*(volatile INT32U *) (CDSP_BASE + 0x17C))
#define R_ISP_LI_HR_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x180))
#define R_ISP_HR_DEPIXCANCEL_THOLD			(*(volatile INT32U *) (CDSP_BASE + 0x184))
#define R_ISP_HR_DENOISE_THOLD				(*(volatile INT32U *) (CDSP_BASE + 0x188))
#define R_ISP_HR_CROSSTALK_THOLD			(*(volatile INT32U *) (CDSP_BASE + 0x18C))
#define R_ISP_HRR_DENOISE_CROSSTALK_WEIGHT	(*(volatile INT32U *) (CDSP_BASE + 0x190))
#define R_ISP_HR_LUT_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x194))
#define R_ISP_IMSIZE_CROSSTALK_WEIGHT		(*(volatile INT32U *) (CDSP_BASE + 0x198))
#define R_ISP_AWB_H_IDX						(*(volatile INT32U *) (CDSP_BASE + 0x19C))
#define R_ISP_AWB_V_IDX						(*(volatile INT32U *) (CDSP_BASE + 0x1A0))
#define R_ISP_AWB_THRESHOLD_12				(*(volatile INT32U *) (CDSP_BASE + 0x1A4))
#define R_ISP_AWB_THRESHOLD_34				(*(volatile INT32U *) (CDSP_BASE + 0x1A8))
#define R_ISP_AWB_THRESHOLD_56				(*(volatile INT32U *) (CDSP_BASE + 0x1AC))
#define R_ISP_AWB_THRESHOLD_78				(*(volatile INT32U *) (CDSP_BASE + 0x1B0))
#define R_ISP_AWB_THRESHOLD_9A				(*(volatile INT32U *) (CDSP_BASE + 0x1B4))
#define R_ISP_AWB_THRESHOLD_B				(*(volatile INT32U *) (CDSP_BASE + 0x1B8))
#define R_ISP_AWB_THRESHOLD_CD				(*(volatile INT32U *) (CDSP_BASE + 0x1BC))
#define R_CDSP_RAW_SUBSAMPLE_SETTING		(*(volatile INT32U *) (CDSP_BASE + 0x200))
#define R_CDSP_RAW_MIRROR_SETTING			(*(volatile INT32U *) (CDSP_BASE + 0x204))
#define R_CDSP_CLAMP_SETTING				(*(volatile INT32U *) (CDSP_BASE + 0x208))
#define R_CDSP_RB_HSIZE						(*(volatile INT32U *) (CDSP_BASE + 0x20C))
#define R_CDSP_RB_HOFFSET					(*(volatile INT32U *) (CDSP_BASE + 0x210))
#define R_CDSP_RB_VSIZE						(*(volatile INT32U *) (CDSP_BASE + 0x214))
#define R_CDSP_RB_VOFFSET					(*(volatile INT32U *) (CDSP_BASE + 0x218))
#define R_CDSP_WDRAM_HOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x21C))
#define R_CDSP_WDRAM_VOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x220))
#define R_CDSP_LINE_INTERVAL				(*(volatile INT32U *) (CDSP_BASE + 0x224))
#define R_CDSP_DO							(*(volatile INT32U *) (CDSP_BASE + 0x228))
#define R_CDSP_TV_MODE						(*(volatile INT32U *) (CDSP_BASE + 0x22C))
#define R_CDSP_WSRAM_THR					(*(volatile INT32U *) (CDSP_BASE + 0x230))
#define R_CDSP_DATA_FORMAT					(*(volatile INT32U *) (CDSP_BASE + 0x240))
#define R_CDSP_GINT							(*(volatile INT32U *) (CDSP_BASE + 0x248))
/*	GP15F Not Support
#define R_Ndenoise_CTRL						(*(volatile INT32U *) (CDSP_BASE + 0x250))
#define R_Ndenoise_Ledge_Set				(*(volatile INT32U *) (CDSP_BASE + 0x254))
#define R_Ndenoise_Ledge_Cof0				(*(volatile INT32U *) (CDSP_BASE + 0x258))
#define R_Ndenoise_Ledge_Cof1				(*(volatile INT32U *) (CDSP_BASE + 0x25C))
#define R_Ndenoise_Ledge_Cof2				(*(volatile INT32U *) (CDSP_BASE + 0x260))
*/
#define R_CDSP_MD_CTRL						(*(volatile INT32U *) (CDSP_BASE + 0x270))
#define R_CDSP_MD_HSIZE						(*(volatile INT32U *) (CDSP_BASE + 0x274))
#define R_CDSP_MD_DMA_SADDR					(*(volatile INT32U *) (CDSP_BASE + 0x278))
#define R_CDSP_MD_DIFF_CNT					(*(volatile INT32U *) (CDSP_BASE + 0x27C))

//sharpen
#define R_CDSP_SP_HPFTH						(*(volatile INT32U *) (CDSP_BASE + 0x288))
#define R_CDSP_SP_CTRL						(*(volatile INT32U *) (CDSP_BASE + 0x28C))
#define R_CDSP_SP_THRD						(*(volatile INT32U *) (CDSP_BASE + 0x290))

// interpolation
#define R_CDSP_INTPL_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x294))

//debug
#define	R_ISP_CHECK_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x2A0))
#define	R_ISP_CHECK_SIZE					(*(volatile INT32U *) (CDSP_BASE + 0x2A4))

// CbCr sup
#if 0 //gp15f not support
#define R_CDSP_CbCrsup_Enandcos4			(*(volatile INT32U *) (CDSP_BASE + 0x2B0))
#define R_CDSP_CbCrsup_csi					(*(volatile INT32U *) (CDSP_BASE + 0x2B4))
#define R_CDSP_CbCrsup_cos					(*(volatile INT32U *) (CDSP_BASE + 0x2B8))
#define R_CDSP_CbCrsup_csslop01				(*(volatile INT32U *) (CDSP_BASE + 0x2BC))
#define R_CDSP_CbCrsup_csslop34				(*(volatile INT32U *) (CDSP_BASE + 0x2C0))
#define R_CDSP_CbCrsup_cbcrth01				(*(volatile INT32U *) (CDSP_BASE + 0x2C4))
#define R_CDSP_CbCrsup_cbcrth34				(*(volatile INT32U *) (CDSP_BASE + 0x2C8))
#endif

//YNLM Ctrl,GP15F
#if 0 //gp15f not support
#define	R_ISP_YNLM_RANGTH					(*(volatile INT32U *)(CDSP_BASE + 0x2CC))
#define	R_ISP_YNLM_PXDTH_RANG0				(*(volatile INT32U *)(CDSP_BASE + 0x2D0))
#define	R_ISP_YNLM_PXDTH_RANG01				(*(volatile INT32U *)(CDSP_BASE + 0x2D4))
#define	R_ISP_YNLM_PXDTH_RANG1				(*(volatile INT32U *)(CDSP_BASE + 0x2D8))
#define	R_ISP_YNLM_PXDTH_RANG2				(*(volatile INT32U *)(CDSP_BASE + 0x2DC))
#define	R_ISP_YNLM_PXDTH_RANG23				(*(volatile INT32U *)(CDSP_BASE + 0x2E0))
#define	R_ISP_YNLM_PXDTH_RANG3				(*(volatile INT32U *)(CDSP_BASE + 0x2E4))
#define	R_ISP_YNLM_PXWT0					(*(volatile INT32U *)(CDSP_BASE + 0x2E8))
#define	R_ISP_YNLM_PXWT1					(*(volatile INT32U *)(CDSP_BASE + 0x2EC))
#endif

//Hybrid Bilateral,GP15F
#define	R_ISP_HBNR_CTRL						(*(volatile INT32U *)(CDSP_BASE + 0x2F0))
#define	R_ISP_HBAJ_CTRL						(*(volatile INT32U *)(CDSP_BASE + 0x2F4))

#define R_CDSP_DMA_YUVABUF_SADDR			(*(volatile INT32U *) (CDSP_BASE + 0x300))
#define R_CDSP_DMA_YUVABUF_HVSIZE			(*(volatile INT32U *) (CDSP_BASE + 0x304))
#define R_CDSP_DMA_YUVBBUF_SADDR			(*(volatile INT32U *) (CDSP_BASE + 0x308))
#define R_CDSP_DMA_YUVBBUF_HVSIZE			(*(volatile INT32U *) (CDSP_BASE + 0x30C))
#define R_CDSP_DMA_RAWBUF_SADDR				(*(volatile INT32U *) (CDSP_BASE + 0x310))
#define R_CDSP_DMA_RAWBUF_HVSIZE			(*(volatile INT32U *) (CDSP_BASE + 0x314))
#define R_CDSP_DMA_RAWBUF_HOFFSET			(*(volatile INT32U *) (CDSP_BASE + 0x318))
#define R_CDSP_DMA_COFG						(*(volatile INT32U *) (CDSP_BASE + 0x324))
#define R_ISP_AWB_RG						(*(volatile INT32U *) (CDSP_BASE + 0x340))
#define R_ISP_AWB_BG						(*(volatile INT32U *) (CDSP_BASE + 0x344))
#define R_ISP_AWB_R							(*(volatile INT32U *) (CDSP_BASE + 0x348))
#define R_ISP_AWB_G							(*(volatile INT32U *) (CDSP_BASE + 0x34C))
#define R_ISP_AWB_B							(*(volatile INT32U *) (CDSP_BASE + 0x350))
#define R_ISP_AWB_PX						(*(volatile INT32U *) (CDSP_BASE + 0x354))
#define R_ISP_AWB_RG_LV						(*(volatile INT32U *) (CDSP_BASE + 0x358))
#define R_ISP_AWB_BG_LV						(*(volatile INT32U *) (CDSP_BASE + 0x35C))
#define R_ISP_AWB_PX_LV						(*(volatile INT32U *) (CDSP_BASE + 0x360))
#define R_CDSP_AWB_WIN_RGGAIN2				(*(volatile INT32U *) (CDSP_BASE + 0x400))
#define R_CDSP_AWB_WIN_BGAIN2				(*(volatile INT32U *) (CDSP_BASE + 0x404))
#define R_CDSP_AE_AWB_WIN_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x408))
#define R_CDSP_AE_WIN_SIZE					(*(volatile INT32U *) (CDSP_BASE + 0x40C))
#define R_CDSP_RGB_WINH_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x410))
#define R_CDSP_RGB_WINV_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x414))
#define R_CDSP_AE_WIN_ABUFADDR				(*(volatile INT32U *) (CDSP_BASE + 0x418))
#define R_CDSP_AE_WIN_BBUFADDR				(*(volatile INT32U *) (CDSP_BASE + 0x41C))
#define R_CDSP_HISTGM_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x420))
#define	R_CDSP_HISTGM_WINSTART				(*(volatile INT32U *) (CDSP_BASE + 0x424))	//gp15f modified
#define	R_CDSP_HISTGM_WINEND				(*(volatile INT32U *) (CDSP_BASE + 0x428))	//gp15f modified
#if 0 //gp15f not support
#define R_CDSP_AF_WIN1_HVOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x42C))
#define R_CDSP_AF_WIN1_HVSIZE				(*(volatile INT32U *) (CDSP_BASE + 0x430))
#define R_CDSP_AF_WIN_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x434))
#define R_CDSP_AF_WIN2_HVOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x438))
#define R_CDSP_AF_WIN3_HVOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x43C))
#endif
//New AWB Win,GP15F
#define	R_ISP_AWBWIN_GDivB_TH				(*(volatile INT32U *) (CDSP_BASE + 0x440))
#define	R_ISP_AWBWIN_GDivR_TH				(*(volatile INT32U *) (CDSP_BASE + 0x444))
#define R_CDSP_AWB_WIN_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x454))
#define R_CDSP_AWB_SPECWIN_Y_THR			(*(volatile INT32U *) (CDSP_BASE + 0x458))
#define R_CDSP_AWB_SPECWIN_UV_THR1			(*(volatile INT32U *) (CDSP_BASE + 0x45C))
#define R_CDSP_AWB_SPECWIN_UV_THR2			(*(volatile INT32U *) (CDSP_BASE + 0x460))
#define R_CDSP_AWB_SPECWIN_UV_THR3			(*(volatile INT32U *) (CDSP_BASE + 0x464))
#define R_CDSP_SUM_CNT1						(*(volatile INT32U *) (CDSP_BASE + 0x468))
#define R_CDSP_SUM_G1_L						(*(volatile INT32U *) (CDSP_BASE + 0x46C))
#define R_CDSP_SUM_G1_H						(*(volatile INT32U *) (CDSP_BASE + 0x470))
#define R_CDSP_SUM_RG1_L					(*(volatile INT32U *) (CDSP_BASE + 0x474))
#define R_CDSP_SUM_RG1_H					(*(volatile INT32U *) (CDSP_BASE + 0x478))
#define R_CDSP_SUM_BG1_L					(*(volatile INT32U *) (CDSP_BASE + 0x47C))
#define R_CDSP_SUM_BG1_H					(*(volatile INT32U *) (CDSP_BASE + 0x480))
#define R_CDSP_SUM_CNT2						(*(volatile INT32U *) (CDSP_BASE + 0x484))
#define R_CDSP_SUM_G2_L						(*(volatile INT32U *) (CDSP_BASE + 0x488))
#define R_CDSP_SUM_G2_H						(*(volatile INT32U *) (CDSP_BASE + 0x48C))
#define R_CDSP_SUM_RG2_L					(*(volatile INT32U *) (CDSP_BASE + 0x490))
#define R_CDSP_SUM_RG2_H					(*(volatile INT32U *) (CDSP_BASE + 0x494))
#define R_CDSP_SUM_BG2_L					(*(volatile INT32U *) (CDSP_BASE + 0x498))
#define R_CDSP_SUM_BG2_H					(*(volatile INT32U *) (CDSP_BASE + 0x49C))
#define R_CDSP_SUM_CNT3						(*(volatile INT32U *) (CDSP_BASE + 0x4A0))
#define R_CDSP_SUM_G3_L						(*(volatile INT32U *) (CDSP_BASE + 0x4A4))
#define R_CDSP_SUM_G3_H						(*(volatile INT32U *) (CDSP_BASE + 0x4A8))
#define R_CDSP_SUM_RG3_L					(*(volatile INT32U *) (CDSP_BASE + 0x4AC))
#define R_CDSP_SUM_RG3_H					(*(volatile INT32U *) (CDSP_BASE + 0x4B0))
#define R_CDSP_SUM_BG3_L					(*(volatile INT32U *) (CDSP_BASE + 0x4B4))
#define R_CDSP_SUM_BG3_H					(*(volatile INT32U *) (CDSP_BASE + 0x4B8))
#if 0
#define R_CDSP_AF_WIN1_HVALUE_L				(*(volatile INT32U *) (CDSP_BASE + 0x4C0))
#define R_CDSP_AF_WIN1_HVALUE_H				(*(volatile INT32U *) (CDSP_BASE + 0x4C4))
#define R_CDSP_AF_WIN1_VVALUE_L				(*(volatile INT32U *) (CDSP_BASE + 0x4C8))
#define R_CDSP_AF_WIN1_VVALUE_H				(*(volatile INT32U *) (CDSP_BASE + 0x4CC))
#define R_CDSP_AF_WIN2_HVALUE_L				(*(volatile INT32U *) (CDSP_BASE + 0x4D0))
#define R_CDSP_AF_WIN2_HVALUE_H				(*(volatile INT32U *) (CDSP_BASE + 0x4D4))
#define R_CDSP_AF_WIN2_VVALUE_L				(*(volatile INT32U *) (CDSP_BASE + 0x4D8))
#define R_CDSP_AF_WIN2_VVALUE_H				(*(volatile INT32U *) (CDSP_BASE + 0x4DC))
#define R_CDSP_AF_WIN3_HVALUE_L				(*(volatile INT32U *) (CDSP_BASE + 0x4E0))
#define R_CDSP_AF_WIN3_HVALUE_H				(*(volatile INT32U *) (CDSP_BASE + 0x4E4))
#define R_CDSP_AF_WIN3_VVALUE_L				(*(volatile INT32U *) (CDSP_BASE + 0x4E8))
#define R_CDSP_AF_WIN3_VVALUE_H				(*(volatile INT32U *) (CDSP_BASE + 0x4EC))
#endif
#define R_CDSP_AEF_WIN_TEST					(*(volatile INT32U *) (CDSP_BASE + 0x4FC))

// front
#define R_CDSP_FRONT_CTRL0					(*(volatile INT32U *) (CDSP_BASE + 0x600))
#define R_CDSP_FLASH_WIDTH					(*(volatile INT32U *) (CDSP_BASE + 0x604))
#define R_CDSP_FLASH_TRIG_NUM				(*(volatile INT32U *) (CDSP_BASE + 0x608))
#define R_CDSP_SNAP_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x60C))
#define R_CDSP_FRONT_CTRL1					(*(volatile INT32U *) (CDSP_BASE + 0x610))
#define R_CDSP_HSYNC_FREDGE					(*(volatile INT32U *) (CDSP_BASE + 0x614))
#define R_CDSP_VSYNC_FREDGE					(*(volatile INT32U *) (CDSP_BASE + 0x618))
#define R_CDSP_FRONT_CTRL2					(*(volatile INT32U *) (CDSP_BASE + 0x61C))
#define R_CDSP_FRAME_H_SETTING				(*(volatile INT32U *) (CDSP_BASE + 0x620))
#define R_CDSP_FRAME_V_SETTING				(*(volatile INT32U *) (CDSP_BASE + 0x624))
#define R_CDSP_TG_LINE_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x628))
#define R_CDSP_FRAME_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x62C))
#define R_CDSP_EXTH_SEPA					(*(volatile INT32U *) (CDSP_BASE + 0x630))
#define R_CDSP_TG_LS_LINE_NUM				(*(volatile INT32U *) (CDSP_BASE + 0x634))
#define R_CDSP_FRONT_CTRL3					(*(volatile INT32U *) (CDSP_BASE + 0x638))
#define R_CDSP_TG_ZERO						(*(volatile INT32U *) (CDSP_BASE + 0x63C))
#define R_CDSP_TG_GPIO_SEL_OEN				(*(volatile INT32U *) (CDSP_BASE + 0x640))
#define R_CDSP_TG_GPIO_OUT_IN				(*(volatile INT32U *) (CDSP_BASE + 0x644))
#define R_CDSP_TG_GPIO_REVENT				(*(volatile INT32U *) (CDSP_BASE + 0x648))
#define R_CDSP_TG_GPIO_FEVENT				(*(volatile INT32U *) (CDSP_BASE + 0x64C))
#define R_CDSP_MIPI_CTRL					(*(volatile INT32U *) (CDSP_BASE + 0x650))
#define R_CDSP_MIPI_HVOFFSET				(*(volatile INT32U *) (CDSP_BASE + 0x654))
#define R_CDSP_MIPI_HVSIZE					(*(volatile INT32U *) (CDSP_BASE + 0x658))
#define R_CDSP_FRONT_CTRL4					(*(volatile INT32U *) (CDSP_BASE + 0x65C))
#define R_CDSP_SONY_SEN_DATA				(*(volatile INT32U *) (CDSP_BASE + 0x660))
#define R_CDSP_FRONT_GCLK					(*(volatile INT32U *) (CDSP_BASE + 0x664))
#define R_CDSP_SEN_CTRL_SIG					(*(volatile INT32U *) (CDSP_BASE + 0x668))
#define R_CDSP_FRONT_INT					(*(volatile INT32U *) (CDSP_BASE + 0x66C))
#define R_CDSP_VD_RFOCC_INT					(*(volatile INT32U *) (CDSP_BASE + 0x670))
#define R_CDSP_INTH_NUM						(*(volatile INT32U *) (CDSP_BASE + 0x674))
#define R_CDSP_FRONT_INTEN					(*(volatile INT32U *) (CDSP_BASE + 0x678))
#define R_CDSP_FRONT_VDRF_INT				(*(volatile INT32U *) (CDSP_BASE + 0x67C))
#define R_CDSP_FRONT_VDRF_INTEN				(*(volatile INT32U *) (CDSP_BASE + 0x680))
#define R_CDSP_SIG_GEN						(*(volatile INT32U *) (CDSP_BASE + 0x684))
#define R_CDSP_FRONT_PROBE_CTRL				(*(volatile INT32U *) (CDSP_BASE + 0x688))
#define R_CDSP_FRONT_DUMMY					(*(volatile INT32U *) (CDSP_BASE + 0x68C))
#define R_CDSP_FPICNT						(*(volatile INT32U *) (CDSP_BASE + 0x690))
#define R_CDSP_EXTRGB						(*(volatile INT32U *) (CDSP_BASE + 0x694))
#define R_CDSP_MACRO_RW						(*(volatile INT32U *) (CDSP_BASE + 0x800))
#define R_CDSP_MACRO_SDRAM_RW				0xD0800800	//(*(volatile INT32U *)(CDSP_BASE+0x800))


/******************************************************************************
 * Rotate: 0xC0240000
 ******************************************************************************/
#define ROTATOR_BASE			((volatile INT32U *) 0xC0240000)
#define R_ROTATOR_BUF_I_ADDR	(*((volatile INT32U *) 0xC0240000))
#define R_ROTATOR_BUF_O_ADDR	(*((volatile INT32U *) 0xC0240004))
#define R_ROTATOR_IMG_WIDTH		(*((volatile INT32U *) 0xC0240008))
#define R_ROTATOR_IMG_HEIGHT	(*((volatile INT32U *) 0xC024000C))
#define R_ROTATOR_CTRL			(*((volatile INT32U *) 0xC0240010))
#define R_ROTATOR_START			(*((volatile INT32U *) 0xC0240014))
#define R_ROTATOR_IRQ_STATUS	(*((volatile INT32U *) 0xC0240018))
#define R_ROTATOR_IRQ_EN		(*((volatile INT32U *) 0xC024001C))
#define R_ROTATOR_BUF_I_ADDR2	(*((volatile INT32U *) 0xC0240020))
#define R_ROTATOR_LINEBUF_EN	(*((volatile INT32U *) 0xC0240100))
#endif // __DRV_L1_SFR_H__
